KR980005590A - METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR - Google Patents

METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR Download PDF

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Publication number
KR980005590A
KR980005590A KR1019960025225A KR19960025225A KR980005590A KR 980005590 A KR980005590 A KR 980005590A KR 1019960025225 A KR1019960025225 A KR 1019960025225A KR 19960025225 A KR19960025225 A KR 19960025225A KR 980005590 A KR980005590 A KR 980005590A
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KR
South Korea
Prior art keywords
metal layer
forming
insulating film
metal wiring
polishing
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KR1019960025225A
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Korean (ko)
Inventor
정인권
부재필
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김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960025225A priority Critical patent/KR980005590A/en
Publication of KR980005590A publication Critical patent/KR980005590A/en

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

신규한 반도체장치의 금속배선 형성방법이 개시되어 있다. 반도체기판 상에 제1절연막을 형성한 후, 금속배선이 형성될 부위의 상기 제1절연막을 식각하여 트렌치를 형성한다. 상기 트렌치가 형성된 결과물 상에 제2절연막을 형성한 후, 상기 트렌치를 완전히 매립할 수 있을 정도의 두께로 금속층을 증착한다. 상기 트렌치의 모서리 부위에 존재하는 상기 제2절연막의 완만한 곡률부위가 완전히 제거될 때까지 상기 금속층을 화학기계연마(CMP) 공정으로 과도하게 연마하여 금속배선을 형성한다. 금속배선의 상부 임계치수를 감소시킬 수 있다.A method of forming a metal wiring of a novel semiconductor device is disclosed. After the first insulating film is formed on the semiconductor substrate, the first insulating film on the portion where the metal wiring is to be formed is etched to form a trench. After forming the second insulating film on the trench formed product, the metal layer is deposited to a thickness sufficient to completely fill the trench. The metal layer is excessively polished by a chemical mechanical polishing (CMP) process until a gentle curvature portion of the second insulating film existing at a corner portion of the trench is completely removed to form a metal wiring. The upper threshold value of the metal wiring can be reduced.

Description

반도체장치의 금속배선 형성방법METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제4도는 본 발명의 제1실시예에 의한 반도체 장치의 배선 형성방법을 설명하기 위한 단면도.FIG. 4 is a sectional view for explaining a wiring forming method of a semiconductor device according to the first embodiment of the present invention; FIG.

Claims (9)

반도체기판상에 제1절연막을 형성하는 단계: 금속배선이 형성될 부위의 상기 제1절연막을 식각하여 트렌치를 형성하는 단계: 상기 트렌치가 형성된 결과물 상에 제2절연막을 형성하는 단계: 상기 트렌치를 완전히 매립할수 있을 정도의 두께로 금속층을 증착하는 단계: 및 상기 트렌치의 모서리 부위에 존재하는 상기 제2절연막의 완만한 곡률부위가 완전히 제거될 때까지 상기 금속층을 화학기계연마(CMP)공정으로 과도하게 연마하여 금속배선을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.Forming a first insulating film on a semiconductor substrate; forming a trench by etching the first insulating film at a portion where a metal wiring is to be formed; forming a second insulating film on the trench formed product; Depositing a metal layer to a thickness sufficient to fully fill the metal layer; and depositing a metal layer over the metal layer through a chemical mechanical polishing (CMP) process until the gentle curvature portion of the second insulating layer present at the edge of the trench is completely removed. And forming a metal wiring by polishing the metal wiring. 제1항에 있어서, 상기 CMP공정시, 상기 금속층을 산화시킬수 있는 산화제 및 이렇게 산화된 금속층을 연마해내는 연마입자로 구성된 연마제를 사용하는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.The method of forming a metal wiring of a semiconductor device according to claim 1, wherein an oxidizing agent capable of oxidizing the metal layer and an abrasive particle comprising abrasive particles for polishing the oxidized metal layer are used in the CMP process. 제1항에 있어서, 상기 금속층은 텅스텐(W),알루미늄(Al), 알루미늄(AI). 알루미늄이 주성분으로 된 화합물, 구리(Cu) 및 구리가 주성분으로 된 화합물의 군에서 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체장치의금속배선 형성방법.The method of claim 1, wherein the metal layer is tungsten (W), aluminum (Al), aluminum (AI). Wherein the metal wiring is formed of any one selected from the group consisting of a compound mainly composed of aluminum, a compound containing copper (Cu) and copper as a main component. 제1항에 있어서, 상기 제2절연막은 실리콘산화막(SiO2), 실리콘화막(SiN), 실리콘산화질화막(SiON), BN 및 폴리머의 군에서 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.2. The semiconductor device according to claim 1, wherein the second insulating film is formed of any one selected from the group consisting of a silicon oxide film (SiO 2 ), a silicon nitride film (SiN), a silicon oxynitride film (SiON) Wire forming method. 반도체기판 상에 제1절연막을 형성하는 단계: 금속배선이 형성될 부위의 상기 제 1절연막을 식각하여 트렌치를 형성하는 단계: 상기 트렌치가 형성된 결과물 상에 제2절연막을 형성하는 단계: 상기 트렌치를 완전히 매립할수 있을 정도의 두께로 금속층을 증착하는 단계: 및 상기 금속층의 CMP용 연마제를 이용하여 상기 제2절연막이 노출될때까지 금속층을 연마한 후, 상기제2절연막의 CMP용 연마제를 이용하여 추가 연마를 진행하여 금속배선을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.Forming a first insulating film on a semiconductor substrate; forming a trench by etching the first insulating film at a portion where a metal wiring is to be formed; forming a second insulating film on the trench formed product; Depositing a metal layer to a thickness sufficient to completely fill the metal layer; and polishing the metal layer until the second insulating layer is exposed using the CMP polishing slurry of the metal layer, and then polishing the metal layer using an abrasive for CMP of the second insulating layer And forming a metal wiring by polishing the metal wiring. 제5항에 있어서, 상기 CMP 공정시, 상기 금속층을 산화시킬 수 있는 산화제 및 이렇게 산화된 금속층을 연마해내는 연마입자로 구성된 연마제를 사용하는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.6. The method of forming a metal wiring of a semiconductor device according to claim 5, wherein an oxidizing agent capable of oxidizing the metal layer and an abrasive particle consisting of abrasive particles for polishing the oxidized metal layer are used in the CMP process. 제5항에 있어서, 상기 금속층은 텅스텐(W), 알루미늄(Al), 알루미늄이 주성분으로 된 화합물, 구리(Cu) 및 구리가 주성분으로 된 화합물의 군에서 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.The semiconductor device according to claim 5, wherein the metal layer is formed of any one selected from the group consisting of tungsten (W), aluminum (Al), a compound mainly composed of aluminum, copper (Cu) A method of forming a metal wiring of a device. 제5항에 있어서, 상기 제2절연막은 리콘산화막(SiO2), 실리콘질화막(SiN), 실리콘산화질화막(SiON), BN 및 폴리머의 군에서 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.The method of claim 5, wherein the second insulating layer is silicon oxide (SiO 2), silicon nitride (SiN), metals of the semiconductor device characterized in that it formed of one selected from the group consisting of a silicon oxynitride film (SiON), BN and polymers Wire forming method. 제5항에 있어서, 상기 제2절연막의 CMP용 연마제는 상기 제2 절연막의 연마속도와 상기 금속층의 연마속도 와의 비가 2 : 1이상이 되는 연마제를 사용하는 것을 특징으로 하는 반도체장치의 금속배선 형성방법.6. The method of manufacturing a semiconductor device according to claim 5, wherein the CMP polishing slurry of the second insulating film uses an abrasive which has a ratio of a polishing rate of the second insulating film to a polishing rate of the metal layer of 2: 1 or more Way. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025225A 1996-06-28 1996-06-28 METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR KR980005590A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030020855A (en) * 2001-09-04 2003-03-10 엔이씨 일렉트로닉스 코포레이션 Method of forming metal wiring line
KR100469338B1 (en) * 1997-12-30 2005-05-17 주식회사 하이닉스반도체 MOS PET Metal Film Formation Method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100469338B1 (en) * 1997-12-30 2005-05-17 주식회사 하이닉스반도체 MOS PET Metal Film Formation Method
KR20030020855A (en) * 2001-09-04 2003-03-10 엔이씨 일렉트로닉스 코포레이션 Method of forming metal wiring line

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