KR980004803A

KR980004803A - Multichannel de-emphasis filter without multiplier

Info

Publication number: KR980004803A
Application number: KR1019960023889A
Authority: KR
Inventors: 염왕섭; 손한웅
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1996-06-26
Filing date: 1996-06-26
Publication date: 1998-03-30

Abstract

본 발명은 디지털 오디오시스템에서 가청영역 주파수내의 신호의 신호대잡음비를 개선하기 위한 필터에 관한 것으로서, 특히 가청여영내의 고주파 신호 성분에 대해 재생시에 가변샘플링 주파수에 대응하는 곱셈기가 없는 다채널 디엠퍼시스 필터에 관한 것이다.The present invention relates to a filter for improving the signal-to-noise ratio of a signal in an audible region frequency in a digital audio system. In particular, the present invention relates to a multi-channel de-emphasis filter without a multiplier corresponding to a variable sampling frequency when reproducing high frequency signal components in an audible region. It is about.

본 발명에 따른 가변샘플링 주파수에 대응하는 곱셈기가 없는 다채널 디엠퍼시스 필터는 곱셈기를 사용하는 경우에 비하여 배럴쉬프트와 가산기로 최적화된 소정의 게인 A,A1,B를 갖는 데이타를 산출하기 때문에 회로의 크기를 줄일 수 있고, 입출력 및 피드백 루프에 지연부를 구성함으로써 다채널 데이터를 처리할 수 있다.The multichannel de-emphasis filter without a multiplier corresponding to the variable sampling frequency according to the present invention produces data having a predetermined gain A, A1, B optimized by a barrel shifter and an adder compared to the case of using a multiplier. The size can be reduced, and multi-channel data can be processed by configuring delays in the input / output and feedback loops.

Description

Multichannel de-emphasis filter without multiplier

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 가변 샘플링 주파수에 대응하는 곱셈기가 없는 다채널 디엠퍼시스 필터의 회로이다.3 is a circuit of a multichannel de-emphasis filter without a multiplier corresponding to a variable sampling frequency according to the present invention.

Claims

A first delay unit which inputs input data and delays data of multiple channels by the number of channels; A data group delay unit for collectively delaying the data output from the first delay unit; A first shift / adder and a second shift / adder for inputting data output from the data group delay unit to adjust amplification of the data; A first adder configured to input and add output data of the second shift / adder and first feedback data; A second delay unit for introducing and delaying the output data of the first adder; A third shift / adder for inputting output data of the second delay unit to adjust amplification of the data to output the first feedback data; A second adder which adds output data of the first adder and data of the first shift / adder; And a second delay section for delaying the data to synchronize other data.

※ Note: The disclosure is based on the initial application.