KR970076817A

KR970076817A - Ferroelectric memory

Info

Publication number: KR970076817A
Application number: KR1019960016304A
Authority: KR
Inventors: 구본재
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1996-05-15
Filing date: 1996-05-15
Publication date: 1997-12-12
Anticipated expiration: 2016-05-15
Also published as: KR0178001B1

Abstract

본 발명은 반도체 메모리에 관한 것으로, 특히, 집적도 및 수명을 향상시킬 수 있는 강유전체 메모리(FRAM : Ferro-electric RAM : 이하 에프램이라 한다.)에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a ferroelectric RAM (FRAM) capable of improving integration and lifetime.

본 발명은 복수의 비트라이쌍들; 복수의 워드라인들; 각 비트라인쌍들에 연결된 복수의 센스 증폭기들; 상기 각 비트라인쌍들에 각각 연결된 복수의 등화 수단들; 상기 각 비트라인쌍의 하나의 비트라인과 각 워드라인의교차부에 하나의 강유전체 캐피시터와 하나의 셀 스위칭 소자로 형성되고, 상기 셀스위칭 소자는 캐피시터의 일측전극과 상기 비트라인 사이에 연결되어 워드라인에 인가되는 신호에 응답하여 스위칭되도록 형성된 복수의 메모리셀들; 상기 복수의 메모리셀들 중 공통 워드라인에 연결된 메모리셀들의 각 강유전체 캐패시터의 타측전극에 공통으로 연결된 복수의 공통전극라인들; 상기 각 비트라인쌍의 다른 하나의 비트라인과 접지 사이에 각각 연결되어 선택된 비트라인을 접지 전압으로 초기화시키는 복수의 tm위칭소자들; 상기 복수의 스위칭 소자들 중 하나를 선택하기 위한 디코더; 및 상기 각 비트라인쌍들 중 상기 스위칭 소자와 연결된 비트라인들에 공통으로 기준전압을 인가하는 공통기준전압공급기를 구비한 것을 특징으로 하여 리드/라이트 동작을 할 수 있도록 함으로서 집적도 및 메모리 수명 연장을 할 수 있다.The present invention relates to a memory device comprising a plurality of bit line pairs; A plurality of word lines; A plurality of sense amplifiers coupled to each bit line pair; A plurality of equalization means coupled to each of the bit line pairs; Wherein each of the bit lines is formed of one ferroelectric capacitor and one cell switching element at the intersection of one bit line and each word line of the pair of bit lines and the cell switching element is connected between one electrode of the capacitor and the bit line, A plurality of memory cells configured to be switched in response to a signal applied to a line; A plurality of common electrode lines commonly connected to the other electrode of each ferroelectric capacitor of the memory cells connected to the common word line among the plurality of memory cells; A plurality of tm matching elements each connected between the other bit line of each bit line pair and the ground to initialize the selected bit line to a ground voltage; A decoder for selecting one of the plurality of switching elements; And a common reference voltage supplier for applying a reference voltage commonly to the bit lines connected to the switching elements among the bit line pairs. In this way, the read / write operation can be performed, can do.

Description

Ferroelectric memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명에 따른 강유전체 메모리의 단위 메모리 구조를 나타낸 회로도, 제3도는 본 발명에 따른 강유전체 메모리의 주요 부분을 나타낸 구성도.FIG. 2 is a circuit diagram showing a unit memory structure of a ferroelectric memory according to the present invention, FIG. 3 is a diagram showing a main part of a ferroelectric memory according to the present invention. FIG.

Claims

A plurality of bit line pairs; A plurality of word lines; A plurality of sense amplifiers coupled to each bit line pair; A plurality of equalization means coupled to each of the bit line pairs; A ferroelectric capacitor and a cell switching element are formed at an intersection of one bit line and each word line of each bit line pair, and the cell switching element is connected between the one electrode of the capacitor and the bit line, A plurality of memory cells configured to be switched in response to a signal applied to a line; A plurality of common electrode lines commonly connected to the other electrode of the ferroelectric capacitor of the memory cells connected to the common word line among the plurality of memory cells; A plurality of switching elements connected between the other bit line and the plate of each bit line pair to initialize the selected bit line to a ground voltage; A decoder for selecting one of the plurality of switching elements; And a common reference voltage supplier for applying a reference voltage commonly to the bit lines connected to the switching element among the bit line pairs.

A plurality of bit line pairs; A plurality of word lines; A plurality of sense amplifiers; A plurality of equalization means; Wherein the word line is formed by one ferroelectric capacitor and one cell switching element at the intersection of one bit line and each word line of each bit line pair and the cell switching element is connected between one bit electrode of the capacitor and the bit line, A plurality of memory cells configured to be switched in response to a signal applied to the memory cell; A plurality of common electrode lines commonly connected to the other electrode of each ferroelectric capacitor of the memory cells connected to the common word line among the plurality of memory cells; A plurality of switching elements each connected between the other bit line of each bit line pair and the ground to initialize the selected bit line to a ground voltage; A decoder for selecting one of the plurality of switching elements; A decoder for always selecting one of the switching elements among the bit line pairs; And a common reference voltage supplier for applying a reference voltage commonly to the bit lines connected to the switching element among the bit line pairs, wherein the ferroelectric memory holds the bit line pairs on the coin via the equalizing means Selecting one word line among the plurality of word lines and initializing a potential of another bit line selected through the decoder to a ground voltage; Applying a first voltage signal to the common electrode line after the initialization and applying a reference voltage to the other bit line through the common reference voltage supplier; And a voltage signal applied to one bit line through a cell switching element turned on by the selected word line and a voltage signal of another bit line having a reference voltage applied after initialization are compared in a sense amplifier, And reading the ferroelectric memory data.

A plurality of bit line pairs; A plurality of word lines; A plurality of sense amplifiers; A plurality of equalization means; A ferroelectric capacitor and a cell switching element are formed at the intersection of one bit line and each word line of each bit line pair and the cell switching element is connected between one bit electrode of the capacitor and the bit line, A plurality of memory cells configured to be switched in response to a signal applied to the memory cell; A plurality of common electrode lines commonly connected to the other side of the rigid dielectric capacitor of the memory cells connected to the common word line among the plurality of memory cells; A plurality of switching elements each connected between the other bit line of each bit line pair and the ground to initialize the selected bit line to a ground voltage; A decoder for selecting one of the plurality of switching elements; And a common reference voltage supplier for applying a reference voltage commonly to the bit lines connected to the switching elements among the bit line pairs, wherein in the ferroelectric memory, Selecting one word line of the plurality of word lines and applying data to the selected bit line pair through the sense amplifier, applying a first voltage signal to the common electrode line, A step of barometric pressure data of the ferroelectric capacitor through a cell switching element turned on by the ferroelectric capacitor; Equalizing the selected bit line pair over the coin by the equalizing means; And initializing the other bit line to the ground voltage through the selected switching element through the decoder when the selection of the word line is completed.

※ Note: It is disclosed by the contents of the first application.