KR970072506A

KR970072506A - Method for manufacturing field emission device

Info

Publication number: KR970072506A
Application number: KR1019960011998A
Authority: KR
Inventors: 주병권; 이윤희; 오명환
Original assignee: 박원훈; 한국과학기술연구원
Priority date: 1996-04-19
Filing date: 1996-04-19
Publication date: 1997-11-07

Abstract

본 발명의 전계방출소자의 제조방법은, 실리콘 기판에, 복수개의 팁을 구비하는 상부와, 상기 상부를 지지하는 지지부와, 상기 상부와 지지부를 연결하는 연결부로 구성되는 수직형 실리콘 기둥을 형성하는 공정과; 상기 수직형 실리콘 기둥 양측의 실리콘 기판 및 상기 수직형 실리콘 기둥 위에 절연물질과 금속물질을 순차적층시킨 후 리프트 오프하여 상기 수직형 실리콘 기둥 양측에 게이트 전극을 형성하는 공정;을 포함하여 이루어지며, 상기 다수개의 팁을 통해 전계방출영역 및 방출 전류밀도를 증가시킬 수 있고, 상기 리프트 오프 공정에 의해 상기 게이트 전극 및 게이트 절연막을 간단하게 자기 정렬시킬 수 있으며, 또한 상기 게이트 전극과 전체 방출용 팁간의 거리를 매우 짧게 함으로써 게이트 구동전압을 현저히 낮출 수 있는 효과가 있다.A method of manufacturing a field emission device of the present invention is a method of manufacturing a field emission device comprising forming a vertical silicon pillar on an upper surface of a silicon substrate having a plurality of tips, a supporting portion supporting the upper portion, and a connecting portion connecting the upper portion and the supporting portion A process; Forming a gate electrode on both sides of the vertical silicon column by successively depositing an insulating material and a metal material on the silicon substrate on both sides of the vertical silicon column and the vertical silicon column, The field emission region and the emission current density can be increased through the plurality of tips, the gate electrode and the gate insulating film can be easily self-aligned by the lift-off process, and the distance between the gate electrode and the entire emission tip The gate driving voltage can be remarkably lowered.

Description

Method for manufacturing field emission device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도의 (가)도 내지 (바)도는 본 발명에 의한 전계방출소자의 제조방법에 따라 순서대로 도시한 단면도들이다.2 (A) and 2 (B) are cross-sectional views sequentially showing the manufacturing method of a field emission device according to the present invention.

Claims

A step of forming a vertical silicon pillar on a silicon substrate with an upper portion having a plurality of tips, a support portion supporting the upper portion, and a connection portion connecting the upper portion and the support portion; Sequentially forming an insulating material and a metal material on the silicon substrate on both sides of the vertical silicon pillar and the vertical silicon pillar, and then lift-off the metal material to form a metal film for the gate electrode on both sides of the vertical silicon pillar Wherein the method comprises the steps of:

The method of claim 1, wherein the step of forming the vertical silicon pillars comprises: forming an etch mask on the silicon substrate; etching the silicon substrate to a predetermined depth by applying the etch mask; Forming a silicon thermally-oxidized film by thermally oxidizing the entire surface of the resulting product after etching, and removing the silicon thermally-oxidized film.

The method of claim 1, wherein the vertical silicon pillar has a horizontal cross-sectional area of the upper portion greater than a horizontal cross-sectional area of the connection portion.

The method of claim 1, wherein the insulating material and the metal material are deposited by an electron beam evaporation method.

3. The method of claim 2, wherein the etching depth of the silicon substrate is about 1 m to 2 m.

The method of claim 1 or 4, wherein the insulating material is deposited to a height of the vertical silicon pillar so that the vertical silicon pillar and the metal film are adjacent to each other at the same height.

※ Note: It is disclosed by the contents of the first application.