KR970068440A - The word line driving circuit - Google Patents

The word line driving circuit Download PDF

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Publication number
KR970068440A
KR970068440A KR1019960007172A KR19960007172A KR970068440A KR 970068440 A KR970068440 A KR 970068440A KR 1019960007172 A KR1019960007172 A KR 1019960007172A KR 19960007172 A KR19960007172 A KR 19960007172A KR 970068440 A KR970068440 A KR 970068440A
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South Korea
Prior art keywords
level
word line
signal
decoder
vdd
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KR1019960007172A
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Korean (ko)
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KR100204792B1 (en
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최견규
전용원
손장섭
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문정환
엘지반도체 주식회사
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Publication of KR970068440A publication Critical patent/KR970068440A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

본 발명은 워드라인 구동회로에 관한 것으로서, 워드라인 구동회로는 메모리소자의 외부로 부터 입력되는 제1어드레스를 코딩하여 위상이 서로 다른 코딩신호(CD)(/CD)를 출력하는 제1디코더와, 상기 제1어드레스에 동기되어 입력되는 제2어드레스가 인에이블되면 동기되어 구동전압(Vdd) 레벨로 천이되고 디스에이블되면 지연수단에 의해 소정 시간 지연되어 접지 레벨로 천이되는 프리-워드라인지연신호(PWLdly)와 인에이블되면 상기 지연수단에 의해 소정 시간 지연된 후 구동전압(Vdd) 레벨로 천이되고 디스에이블되면 동기되어 접지 레벨로 천이되는 프리-워드라인신호(PWL)를 출력하는 제2디코더와, 상기 제2디코더로 부터 입력되는 프리-워드라인 신호(PWL)에 동기되어 내부 승압전압(Vpp) 레벨 또는 구동전압(Vdd) 레벨로 레벨이 쉬프팅되는 프리-워드라인 구동신호(PWLD)를 출력하는 레벨쉬프터와, 상기 코딩신호(CD)(/CD)에 따라 워드라인(WL)을 상기 프리-워드라인지연신호(PWLdly)로 1차 프리차지시켜 세트시키거나 또는 접지시켜 리세트시키는 구동부와, 상기 세트시 프리-워드 라인구동신호(PWLD)에 의해 상기 1차 프리차지된 워드라인(WL)을 구동전압(Vdd)으로 2차 프리차지 시킨 후 내부 승압전압(Vpp)으로 순차적으로 승압하고, 리세트시 내부 승압전압(Vpp)레벨에서 구동전압(Vdd) 레벨을 겨쳐 접지 레벨로 순차적으로 감압시키는 레벨조절부를 포함한다. 따라서, 워드라인을 세트시킬때 구동전압(Vdd)레벨로 충전한 후 내부 승압전압(Vpp) 레벨로 충전하고 리세트 시킬 때 내부 승압전압(Vpp)레벨에서 구동전압(Vdd)레벨로 감압시킨 후 접지 레벨로 감압시키므로 내부 승압전압(Vpp)의 사용을 줄일 수 있을 뿐만 아니라 전류 소모를 줄일 수 있다.A word line driving circuit includes a first decoder for coding a first address inputted from the outside of a memory device and outputting a coded signal CD / CD having a different phase, A pre-word line delay signal (Vdd) that transitions to a driving voltage (Vdd) level when a second address input in synchronization with the first address is enabled, A second decoder for outputting a pre-word line signal PWL that is transitioned to a driving voltage (Vdd) level after being delayed by the delay means for a predetermined time when enabled, and is synchronized to a ground level when disabled, , A pre-word line (Vpp) level shifted to the level of the internal boost voltage (Vpp) or the drive voltage (Vdd) in synchronization with the pre-word line signal (PWL) input from the second decoder A level shifter for outputting the same signal PWLD and a first precharge circuit for precharging the word line WL with the pre-word line delay signal PWLdly according to the coding signal CD / CD, A precharging circuit for precharging the first precharged word line WL with a driving voltage Vdd by the pre-word line driving signal PWLD at the time of setting, And a level adjusting unit for sequentially reducing the driving voltage (Vdd) level to the ground level at the internal boost voltage (Vpp) level at the time of reset. Therefore, when the word line is set and charged to the level of the internal step-up voltage Vpp after resetting to the level of the drive voltage Vdd at the level of the internal step-up voltage Vpp By reducing the voltage to the ground level, the use of the internal step-up voltage Vpp can be reduced and current consumption can be reduced.

Description

워드라인 구동회로The word line driving circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명에 따른 워드라인 구동회로도, 제2도 (A)~(I)는 제1도에 도시된 워드라인 구동회로의 동작파형도.FIG. 1 is a word line driving circuit diagram according to the present invention, and FIGS. 2 (A) to 2 (I) are operational waveform diagrams of a word line driving circuit shown in FIG.

Claims (6)

메모리소자의 외부로 부터 입력되는 제1어드레스를 코딩하여 위상이 서로 다른 코딩신호(CD)(/CD)를 출력하는 제1디코더와, 상기 제1어드레스에 동기되어 입력되는 제2어드레스가 인에이블되면 동기되어 구동전압 (Vdd) 레벨로 천이되고 디스에이블되면 지연수단에 의해 소정 시간 지연되어 접지 레벨로 천이되는 프리-워드라인지연신호(PWLdly)와 인에이블되면 상기 지연수단에 의해 소정 시간 지연된 후 구동전압(Vdd)레벨로 천이되고 디스에이블되면 동기되어 접지 레벨로 천이되는 프리-워드라인신호(PWL)를 출력하는 제2디코더와, 상기 제2디코더로부터 입력되는 프리-워드라인 신호(PWL)에 동기되어 내부 승압전압(Vpp) 레벨 또는 구동전압(Vdd) 레벨로 레벨이 쉬프팅되는 프리-워드라인 구동신호(PWLD)를 출력하는 레벨쉬프터와, 상기 코딩신호(CD)(/CD)에 따라 워드라인(WL)을 상기 프리-워드라인지연신호 (PWLdly)로 1차 프리차지시켜 세트시키거나 또는 접지시켜 리세트시키는 구동부와, 상기 세트시 프리-워드 라인구동신호(PWLD)에 의해 상기 1차 프리차지된 워드라인(WL)을 구동전압(Vdd)으로 2차 프리차지 시킨 후 내부 승압전압(Vpp)으로 순차적으로 승압하고, 리세트시 내부 승압전압(Vpp)레벨에서 구동전압(Vdd)레벨을 겨쳐 접지 레벨로 순차적으로 감압시키는 레벨조절부를 포함하는 워드라인 구동회로.A first decoder which codes a first address inputted from the outside of the memory device and outputs a coded signal CD / CD whose phases are different from each other, and a second decoder which inputs a second address synchronized with the first address, Word line delay signal PWLdly which is synchronized with the pre-word line delay signal PWLdly which is transited to the driving voltage Vdd level and is disabled when the signal is disabled by the delay means for a predetermined time and then to the ground level, A second decoder for outputting a pre-word line signal PWL that transitions to a driving voltage Vdd level and is synchronized to a ground level when the second decoder is disabled; A level shifter for outputting a pre-word line drive signal PWLD whose level is shifted to a level of an internal boost voltage Vpp or a drive voltage Vdd in synchronization with the coded signal CD /Word line driving signal PWLD to set the pre-word line delay signal PWLdly to the pre-word line delay signal PWLdly, The precharged word line WL is secondarily precharged with the driving voltage Vdd and then stepped up to the internal step-up voltage Vpp sequentially and the drive voltage Vdd at the level of the internal step- And a level adjuster for sequentially decreasing the level to the ground level. 제1항에 있어서, 상기 제2디코더는 제2어드레스가 일측입력단에 직접, 그리고, 타측입력단에 지연수단에 의해 소정 시간 지연되어 각각 입력되는 노아게이트 및 낸드게이트로 이루어진.2. The nonvolatile memory according to claim 1, wherein the second decoder comprises a NOR gate and a NAND gate to which a second address is directly input to one input terminal and the other input terminal is delayed by a delay means for a predetermined time, respectively. 제2항에 있어서, 상기 제2디코더는 노아게이트의 출력신호를 반전시켜 프리-워드라인지연신호(PWLdly)를 출력하는.3. The method of claim 2, wherein the second decoder inverts an output signal of the NOR gate to output a pre-word line delay signal (PWLdly). 제2항에 있어서, 상기 제2디코더는 낸드게이트의 출력신호를 반전시켜 프리-워드라인신호(PWL)를 출력하는,3. The method of claim 2, wherein the second decoder inverts an output signal of the NAND gate to output a pre-word line signal (PWL) 제1항에 있어서, 상기 레벨쉬프터는 프리-워드라인신호(PWL)에 의해 선택적으로 ‘턴-온’ 되어 상기 프리-워드라인구동신호(PWLD)의 레벨을 내부 승압전압(Vpp) 또는 구동전압(Vdd)의 상태가 되도록 레벨을 쉬프팅하는 P 및 N모스트랜지스터를 포함하는.The level shifter according to claim 1, wherein the level shifter is selectively turned on by a pre-word line signal (PWL) so that the level of the pre-word line driving signal (PWLD) And a P and N-MOS transistor for shifting the level to a state of (Vdd). 제5항에 있어서, 상기 레벨쉬프터는 승압시 내부 승압전압(Vpp)이 순간적으로 접지 레벨이되는 래치-업(latch-up)을 방비하는 인버터를 더 포함하는.6. The semiconductor memory device according to claim 5, wherein the level shifter further includes an inverter for preventing a latch-up in which an internal boost voltage (Vpp) instantaneously becomes a ground level during a boost. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960007172A 1996-03-18 1996-03-18 Word line driving circuit KR100204792B1 (en)

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KR100204792B1 KR100204792B1 (en) 1999-06-15

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US7920429B2 (en) 2007-03-30 2011-04-05 Hynix Semiconductor Inc. Semiconductor memory device for reducing power consumption
KR100906647B1 (en) * 2007-03-30 2009-07-07 주식회사 하이닉스반도체 Semiconductor memory apparatus for reducing power consumption

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