KR970067618A - Silicon-on-insulator (SOI) device and manufacturing method thereof - Google Patents

Abstract

A novel silicon-on-insulator device and its manufacturing method are disclosed. A channel of the first conductivity type and a source / drain of the second conductivity type are formed on the surface of the silicon layer formed on the semiconductor substrate via the buried insulating layer. An impurity layer of a high concentration first conductivity type is formed under the first conductive type channel. In addition, a low concentration second conductivity type impurity layer can be further formed at the boundary between the source and the channel below the second conductive type source. The floating body effect can be improved by reducing the current gain of the parasitic bipolar transistor.

Description

Silicon-on-insulator (SOI) device and manufacturing method thereof

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FIG. 2 is a cross-sectional view of an SOI device according to the present invention. FIG.

Claims (10)

A silicon layer formed on the semiconductor substrate via an embedded insulating layer; And a source / drain of a first conductive type formed in a surface of the silicon layer and a source / drain of a second conductive type, wherein an impurity layer of a high concentration first conductive type is formed under the first conductive type channel Lt; RTI ID = 0.0 > silicon-on-insulator < / RTI > The silicon-on-insulator device according to claim 1, further comprising a low concentration second conductivity type impurity layer formed at a boundary between the source and the channel under the second conductive type source. The silicon-on-insulator device according to claim 2, wherein the source of the second conductivity type is formed of any one of N ^- type, and the impurity layer of the low concentration second conductivity type is formed of N ^- type. 3. The silicon-on-insulator device according to claim 1 or 2, further comprising: a low concentration second conductivity type impurity layer formed at a boundary between the drain and the channel below the second conductivity type drain. The silicon-on-insulator according to claim 4, wherein the drain of the second conductivity type is formed of one of an N ^- type and an N ⁺ type, and the impurity layer of the low concentration second conductivity type is formed of an N ^- - Insulator element. Forming a silicon layer on a semiconductor substrate via an embedded insulating layer; Implanting an impurity of a first conductivity type to form a channel region in the silicon layer and forming a high concentration first conductivity type impurity layer under the channel; Forming a gate electrode on a channel region of the silicon layer via a gate insulating film; And forming a source and a drain in the silicon layer by ion implanting a first impurity of a second conductivity type using the gate electrode as a mask. The method according to claim 6, wherein the forming of the channel region and the impurity layer of the first conductivity type with a high concentration further comprises the step of forming an impurity of the first conductivity type for adjusting the threshold voltage on the entire surface of the silicon layer, Wherein a channel region and an impurity layer of a high concentration first conductivity type are formed at the same time by implanting ions while matching a projection range to an interface. 7. The method of claim 6, wherein the forming of the channel region and the impurity layer of the high concentration first conductivity type comprises implanting a first impurity of the first conductivity type for controlling the threshold voltage on the entire surface of the silicon, ; And forming a high concentration first conductivity type impurity layer below the channel region by ion implanting a second impurity of the first conductivity type with the projection range aligned with the interface between the silicon layer and the embedded insulating layer Of the silicon-on-insulator element. 7. The method of claim 6, further comprising the step of implanting a second impurity of a second conductivity type into the source region after the step of forming the source and drain, thereby forming a low concentration second conductivity type And forming an impurity layer on the silicon-on-insulator layer. 10. The method of manufacturing a silicon-on-insulator element according to claim 9, wherein the second impurity of the second conductivity type is also implanted into the drain region. ※ Note: It is disclosed by the contents of the first application.