KR970067353A

KR970067353A - Semiconductor memory device

Info

Publication number: KR970067353A
Application number: KR1019960006022A
Authority: KR
Inventors: 조정호
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1996-03-08
Filing date: 1996-03-08
Publication date: 1997-10-13

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

반도체 메모리.Semiconductor memory.

2. 발명이 해결하려고 하는 기술적 과제2. Technical Challenges to be Solved by the Invention

디램 소자의 센싱 동작 중에 높은 전류가 발생되어 데이터 센싱용 라인에 노이즈를 발생시킨다는 문제점을 해결하고자 함.And to solve the problem that a high current is generated during the sensing operation of the DRAM device to generate noise in the data sensing line.

3. 발명의 해결방법의 요지3. The point of the solution of the invention

각 데이터 입출력 블럭의 워드 라인 인에이블(Word Line Enable) 동작이 순차적으로 이루어지도록 함으로써 데이터 센싱용 라인의 노이즈를 감소시킬 수 있도록 함.The word line enable operation of each data input / output block is sequentially performed so that the noise of the data sensing line can be reduced.

4. 발명의 중요한 용도4. Important Uses of the Invention

반도체 메모리, 특히 다수의 입출력 블록을 포함하는 DRAM 소자에 이용됨.Semiconductor memory, especially used in DRAM devices including a plurality of input / output blocks.

Description

Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제4도는 본 발명의 한 실시예에 따른 16M DRAM의 64개 블록 중 1개의 블록을 도시하는 도면, 제5도의 (a)(b)(c)는 제4도의 지연 회로의 한 실시예를 도시하는 도면, 제6도는 본 발명의 한 실시예에 따른 피크 전류의 감소 정도를 설명하기 위한 도면.FIG. 4 shows one block of 64 blocks of a 16M DRAM according to an embodiment of the present invention. FIGS. 5a, 5b and 5c illustrate an embodiment of the delay circuit of FIG. FIG. 6 is a diagram for explaining a degree of decrease in peak current according to an embodiment of the present invention; FIG.

Claims

A semiconductor memory device comprising a predetermined decoder and a plurality of word line driving circuits and a plurality of data input / output blocks for enabling two or more word lines depending on whether the decoder is decoded, the semiconductor memory device comprising: And a first word line driving circuit connected to the word line driving circuit of the first word line driving circuit and generating second signals whose delay is delayed by a predetermined time, And a plurality of delay circuits for sequentially enabling the word lines of the data input / output block by applying the plurality of word line driving circuits to the plurality of word line driving circuits.

The semiconductor memory device according to claim 1, wherein the delay circuit is constituted by using an inverter.

The semiconductor memory device according to claim 1, wherein the delay circuit is constituted by using a capacitor.

The semiconductor memory device according to claim 1, wherein the delay circuit is formed by combining an inverter and a capacitor.

A first and a second decoder for decoding each word line of the first and second memory array blocks, a first and a second decoder for decoding the first and second memory array blocks, And first and second word line driving circuits which are correspondingly connected between a first decoder and a second decoder to activate each word line, the semiconductor memory device further comprising: a connection between the second decoder and the second word line driving circuit And delay means for delaying said first word line by a predetermined time to activate said second word line.

※ Note: It is disclosed by the contents of the first application.