KR970059877A - Refresh timing generating circuit - Google Patents

Refresh timing generating circuit Download PDF

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Publication number
KR970059877A
KR970059877A KR1019960000839A KR19960000839A KR970059877A KR 970059877 A KR970059877 A KR 970059877A KR 1019960000839 A KR1019960000839 A KR 1019960000839A KR 19960000839 A KR19960000839 A KR 19960000839A KR 970059877 A KR970059877 A KR 970059877A
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KR
South Korea
Prior art keywords
signal
comparison output
generating
output signal
state
Prior art date
Application number
KR1019960000839A
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Korean (ko)
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KR0174512B1 (en
Inventor
김상봉
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960000839A priority Critical patent/KR0174512B1/en
Publication of KR970059877A publication Critical patent/KR970059877A/en
Application granted granted Critical
Publication of KR0174512B1 publication Critical patent/KR0174512B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

본 발명은 리플레쉬 타이밍 발생회로를 공개한다. 그 회로는 제1상태에서 제2상태로 천이시에 열 어드레스 스트로우브 신호를 셋트하기 위한 제1신호 발생수단, 상기 제1상태가 아닌 경우에 인에이블되고 계수를 하기 위한 계수수단, 제3, 4, 및 2상태에 해당하는 상기 계수수단의 계수값을 저장하기 위한 제1, 2, 3저장수단들, 상기 계수수단의 계수값과 상기 저장수단들의 값을 비교하여 제1, 2, 및 3비교 출력신호를 발생하고 상기 제2비교 출력신호에 응답하여 상기 제1신호 발생수단을 리셋트하기 위한 제1, 2, 3비교수단들, 상기 제1, 2, 및 3비교수단들의 값에 응답하여 상기 계수수단을 리셋트하기 위한 리셋트 수단, 및 상기 제1비교 출력신호에 응답하여 셋트되고, 상기 제3비교 출력신호에 응답하여 리셋트되어 행 어드레스 스트로우브 신호를 발생하기 위한 제2신호 발생수단으로 구성되어 있다. 따라서, 사용자가 동적 메모리 장치의 사양을 바꾸더라도 바뀐 동적 메모리 장치의 사양을 만족하는 리플레쉬 타이밍 신호를 발생할 수가 있다.The present invention discloses a refresh timing generating circuit. The circuit includes first signal generating means for setting a column address strobe signal at transition from a first state to a second state, counting means enabled and counted in the non-first state, First, second and third storage means for storing the coefficient values of the counting means corresponding to the first, second, third, fourth, and second states, comparing the count values of the counting means with the values of the storing means, First, second and third comparison means for generating a comparison output signal and for resetting said first signal generation means in response to said second comparison output signal; And reset means responsive to said third comparison output signal for generating a row address strobe signal, said reset means being responsive to said first comparison output signal for resetting said count means, And generating means. Therefore, even if the user changes the specification of the dynamic memory device, it is possible to generate a refresh timing signal satisfying the specification of the changed dynamic memory device.

Description

리플레쉬 타이밍 발생회로Refresh timing generating circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명의 프로그램이 가능한 리플레쉬 타이밍 발생회로의 회로도이다.FIG. 2 is a circuit diagram of a refresh timing generating circuit that can be programmed by the present invention. FIG.

제3도는 제2도에 나타낸 회로의 출력파형을 나타내는 것이다.Figure 3 shows the output waveform of the circuit shown in Figure 2.

Claims (1)

제1상태에서 제2상태로 천이시에 열 어드레스 스트로우브 신호를 셋트하기 위한 제1신호 발생수단; 상기 제1상태가 아닌 경우에 인에이블되고 계수를 하기 위한 계수수단; 제3, 4, 및 2상태에 해당하는 상기 계수수단의 계수값을 저장하기 위한 제1, 2, 3저장수단들; 상기 계수수단의 계수값과 상기 저장수단들의 값을 비교하여 제1, 2, 및 3비교 출력신호를 발생하고 상기 제2비교 출력신호에 응답하여 상기 제1신호 발생수단을 리셋트하기 위한 제1, 2, 3비교수단들; 상기 제1, 2, 및 3비교수단들의 값에 응답하여 상기 계수수단을 리셋트하기 위한 리셋트 수단; 및 상기 제1비교 출력신호에 응답하여 셋트되고, 상기 제3비교 출력신호에 응답하여 리셋트되어 행 어드레스 스트로우브 신호를 발생하기 위한 제2신호 발생수단을 구비한 것을 특징으로 하는 리플레쉬 타이밍 발생회로.First signal generating means for setting a column address strobe signal at a transition from a first state to a second state; Counting means for enabling and counting if not in said first state; First, second, and third storage means for storing the coefficient values of the counting means corresponding to the third, fourth, and second states; Second and third comparison output signals by comparing the count values of the counting means with the values of the storage means and for resetting the first signal generating means in response to the second comparison output signal, , 2, 3 comparison means; Reset means for resetting said counting means in response to values of said first, second and third comparing means; And second signal generating means for generating a row address strobe signal in response to the first comparison output signal and reset in response to the third comparison output signal. Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960000839A 1996-01-17 1996-01-17 Refresh Timing Generation Circuit KR0174512B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960000839A KR0174512B1 (en) 1996-01-17 1996-01-17 Refresh Timing Generation Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960000839A KR0174512B1 (en) 1996-01-17 1996-01-17 Refresh Timing Generation Circuit

Publications (2)

Publication Number Publication Date
KR970059877A true KR970059877A (en) 1997-08-12
KR0174512B1 KR0174512B1 (en) 1999-04-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960000839A KR0174512B1 (en) 1996-01-17 1996-01-17 Refresh Timing Generation Circuit

Country Status (1)

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KR (1) KR0174512B1 (en)

Also Published As

Publication number Publication date
KR0174512B1 (en) 1999-04-01

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