KR970059751A - The hysteresis circuit of the received signal level detector - Google Patents

The hysteresis circuit of the received signal level detector Download PDF

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Publication number
KR970059751A
KR970059751A KR1019960001310A KR19960001310A KR970059751A KR 970059751 A KR970059751 A KR 970059751A KR 1019960001310 A KR1019960001310 A KR 1019960001310A KR 19960001310 A KR19960001310 A KR 19960001310A KR 970059751 A KR970059751 A KR 970059751A
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KR
South Korea
Prior art keywords
received signal
hysteresis
level detector
mosfet
feedback loop
Prior art date
Application number
KR1019960001310A
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Korean (ko)
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KR100190852B1 (en
Inventor
김정호
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960001310A priority Critical patent/KR100190852B1/en
Publication of KR970059751A publication Critical patent/KR970059751A/en
Application granted granted Critical
Publication of KR100190852B1 publication Critical patent/KR100190852B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/20—Monitoring; Testing of receivers

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

본 발명은 수신기에 있어서, 집적 회로 내에서 구현할 수 있는 액티브소자를 이용하여 궤환을 걸어 전원전압 변동에 일정한 히스테라시스 특성을 얻도록 하기 위한 수신 신호 레벨 검출기의 히스테리시스 회로에 관한 것으로, 신호 입력단(1)으로 입력되는 수신신호의 레벨의 검출하여 신호출력단(2)으로 출력하는 수신신호레벨검출기의 히스테리시스 회로에 있어서, 상기 신호 입력단(1)과 신호 출력단(2)에 연결되고 액티브소자로 구성되어 히스테리시스 특성을 부가하는 궤환 루프(3)를 포함하여 구성된다.따라서 본 발명은 소자의 면적만큼으로 궤환 루프를 구성할 수 있으며, 전원 전압변동에 일정한 히스테리시스 특성을 얻을 수 있는 효과가 있다.The present invention relates to a hysteresis circuit of a received signal level detector for obtaining a constant hysteresis characteristic with respect to a power supply voltage fluctuation by applying feedback using an active element which can be implemented in an integrated circuit, 1), and outputs the detected level of the received signal to a signal output stage (2), the hysteresis circuit comprising: an active element connected to the signal input terminal (1) and the signal output terminal (2) And a feedback loop 3 for adding a hysteresis characteristic. Therefore, the present invention can constitute a feedback loop as much as the area of the device, and has the effect of obtaining a constant hysteresis characteristic with respect to power supply voltage fluctuation.

Description

수신 신호 레벨 검출기의 히스테리시스 회로The hysteresis circuit of the received signal level detector

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명에 의한 수신 신호 레벨 검출기의 히스테리시스 회로의 구성점.FIG. 2 is a constitutional point of a hysteresis circuit of a received signal level detector according to the present invention; FIG.

Claims (3)

신호 입력단(1)으로 입력되는 수신신호의 레벨을 검출하여 신호출력단(2)으로 출력하는 수신 신호 레벨 검출기의 히스테리시스 회로에 있어서, 상기 신호 입력단(1)과 신호 출력단(2)에 연결되고 액티브소자로 구성되어 히스테리시스 구성을 부가하는 궤환 루프(3)를 포함하여 구성되는 것을 특징으로 하는 수신 신호 레벨 검출기의 히스테리시스 회로.A hysteresis circuit of a received signal level detector for detecting a level of a received signal inputted to a signal input terminal (1) and outputting the detected level to a signal output terminal (2) And a feedback loop (3) for adding a hysteresis configuration to the hysteresis loop of the received signal level detector. 제1항에 있어서, 상기 궤환 루프(3)는 상기 신호 출력단(2)에 게이트가 연결되고 전원에 소오스가 연결된 제 1MOSFET(M1) 및 상기 제MOSFET(M1)의 드레인과 상기 신호 입력단(1)에 연결된 전류 미러(4)를 포함하여 구성되는 것을 특징으로 하는 수신 신호 레벨검출기의 히스테리시스 회로.The feedback loop (3) according to claim 1, wherein the feedback loop (3) comprises a first MOSFET (M1) having a gate connected to the signal output terminal (2) and a source connected to a power source, And a current mirror (4) connected to the current mirror. 제2항에 있어서, 상기 전류 미러(4)는 상기 제1MOSFET(M1)의 드레인에 드레인과 게이트가 연결되고 접지에 소오스가 연결된 제2MOSFET(M2) 및 상기 제 1MOSFET(M1)제의 드레인에 게이트가 연결되고 상기신호 입력단(1)에 드레인이 연결되고 접지에 소오스가 연결된 제3MOSFET(M3) 을 포함하여 구성되는 것을 특징으로 하는 수신 신호 레벨 검출기의 히스테리시스 회로.The current mirror according to claim 2, wherein the current mirror (4) comprises a second MOSFET (M2) having a drain and a gate connected to a drain of the first MOSFET (M1) and a source connected to a ground, And a third MOSFET (M3) having a drain connected to the signal input terminal (1) and a source connected to a ground, and a third MOSFET (M3) connected to the ground. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960001310A 1996-01-22 1996-01-22 Hysteresis circuit for receive signal level detector KR100190852B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960001310A KR100190852B1 (en) 1996-01-22 1996-01-22 Hysteresis circuit for receive signal level detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960001310A KR100190852B1 (en) 1996-01-22 1996-01-22 Hysteresis circuit for receive signal level detector

Publications (2)

Publication Number Publication Date
KR970059751A true KR970059751A (en) 1997-08-12
KR100190852B1 KR100190852B1 (en) 1999-06-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960001310A KR100190852B1 (en) 1996-01-22 1996-01-22 Hysteresis circuit for receive signal level detector

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020051983A (en) * 2000-12-23 2002-07-02 양윤홍 Key pad of portable wireless phone and the method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020051983A (en) * 2000-12-23 2002-07-02 양윤홍 Key pad of portable wireless phone and the method

Also Published As

Publication number Publication date
KR100190852B1 (en) 1999-06-01

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