KR970056047A - Independent control channel shift clock signal generator during uplink of personal communication terminal - Google Patents

Independent control channel shift clock signal generator during uplink of personal communication terminal Download PDF

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Publication number
KR970056047A
KR970056047A KR1019950071090A KR19950071090A KR970056047A KR 970056047 A KR970056047 A KR 970056047A KR 1019950071090 A KR1019950071090 A KR 1019950071090A KR 19950071090 A KR19950071090 A KR 19950071090A KR 970056047 A KR970056047 A KR 970056047A
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KR
South Korea
Prior art keywords
time slot
signal
bit
frame
control channel
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Application number
KR1019950071090A
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Korean (ko)
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KR0179207B1 (en
Inventor
곽재봉
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유기범
대우통신주식회사
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Priority to KR1019950071090A priority Critical patent/KR0179207B1/en
Publication of KR970056047A publication Critical patent/KR970056047A/en
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Publication of KR0179207B1 publication Critical patent/KR0179207B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0694—Synchronisation in a TDMA node, e.g. TTP
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1694—Allocation of channels in TDM/TDMA networks, e.g. distributed multiplexers

Abstract

본 발명은 단말기에서 기지국으로 독립제어채널(SDCCH)에 대한 제어데이터를 전송함에 있어서 기지국을 통해 할당받은 독립제어채널번호와 자체적으로 생성한 13MHz의 기준클록을 근거로 독립제어채널에 대한 시프트 클록신호를 생성할 수 있도록 된 개인통신용 단말기의 업링크시 독립제어채널 시프트 클록신호 발생장치에 관한 것으로, 이는 13MHz의 클록을 기준으로 하여 각 데이터 비트를 48클록의 길이로 함과 더불어, 156.25비트로 하나의 타임슬롯을 구성하도록 된 개인통신 시스템에 있어서, 13MHz의 기준클록과 프레임개시신호를 근거로 비트동기신호를 생성한 다음 이 비트동기신호를 근거로 타임슬롯동기신호와 148비트신호를 생성하게 된다. 이어, 이 타임슬롯동기신호를 계수하여 현재의 타임슬롯번호를 산정한 다음 이 타임슬롯번호를 근거로 0-타임슬롯 스트로브신호와 프레임동기신호를 생성하여 이 프레임동기신호를 계수하여 프레임번호를 산정하게 된다. 이어, 이 프레임번호데이터와 상기 148비트신호 및 기지국을 통해 할당된 독립제어채널번호를 근거로 독립제어채널에 대한 시프트 클록신호를 발생할 수 있게 된다.The present invention provides a shift clock signal for an independent control channel based on an independent control channel number assigned through the base station and a 13 MHz reference clock generated by the base station in transmitting control data for the independent control channel (SDCCH) from the terminal to the base station. The independent control channel shift clock signal generator in the uplink of a personal communication terminal capable of generating a signal, which is based on a clock of 13 MHz, each data bit is 48 clocks long, and one 156.25 bits In a personal communication system configured to configure a time slot, a bit synchronization signal is generated based on a 13 MHz reference clock and a frame start signal, and then a time slot synchronization signal and a 148 bit signal are generated based on the bit synchronization signal. Next, the current time slot number is calculated by counting the time slot synchronization signal, and then a 0-time slot strobe signal and a frame synchronization signal are generated based on the time slot number, and the frame synchronization signal is counted to calculate the frame number. Done. Subsequently, the shift clock signal for the independent control channel can be generated based on the frame number data, the 148-bit signal, and the independent control channel number assigned through the base station.

Description

개인통신용 단말기의 업링크시 독립제어채널 쉬프트 클록신호 발생장치Independent control channel shift clock signal generator during uplink of personal communication terminal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명의 1실시예에 따른 개인통신용 단말기의 업링크시 독립제어채널 쉬프트 클록신호 발생장치의 구성을 나타낸 회로구성도.5 is a circuit diagram showing the configuration of an independent control channel shift clock signal generator in the uplink of a personal communication terminal according to an embodiment of the present invention.

Claims (1)

13MHz의 클록을 기준으로 하여 각 데이터 비트를 48클록의 길이로 함과 더불어, 156.25비트로 하나의 타임슬롯을 구성하도록 된 개인통신 시스템에 있어서, 13MHz의 기준클록을 생성하는 클록발생수단과, 상기 기준클록과 프레임개시신호를 근거로 비트동기신호를 생성하는 비트동기신호 발생수단, 상기 비트동기신호와 기준클록을 근거로 타임슬롯동기신호를 생성하는 타임슬롯동기신호 발생수단, 상기 비트동기신호와 기준클록을 근거로 148비트신호를 생성하는 148비트신호 발생수단, 상기 타임슬롯동기신호를 계수하여 현재의 타임슬롯번호를 출력하는 타임슬롯번호 계수수단, 상기 타임슬롯번호 계수수단에 의해 계수된 타임슬롯번호를 근거로 1번째 타임슬롯에 대응하는 스트로브신호를 출력하는 타임슬롯 스트로브신호 발생수단, 상기 타임슬롯번호 계수수단으로부터 출력되는 타임슬롯번호를 근거로 프레임동기신호를 출력하는 프레임동기신호 생성수단, 상기 프레임동기신호 생성수단으로부터 출력되는 프레임동기신호를 계수하여 프레임번호데이터를 출력하는 프레임번호 계수수단, 기지국을 통해 할당된 독립제어채널번호데이터를 저장하는 래치수단, 상기 래치수단으로부터의 출력신호를 근거로 소정의 기준데이터를 생성하는 기준데이터출력수단, 상기 148비트신호와 0-타임슬롯 스트로브신호를 근거로 0-타임슬롯의 148비트신호를 발생하는 0-타임슬롯 148비트신호 발생수단 및, 상기 프레임번호 계수수단에 의해 계수된 프레임번호데이터와 상기 기준데이터출력수단에 의해 설정된 기준데이터를 비교하고, 양 데이터 값이 일치하는 기간의 출력신호와 상기 0-타임슬롯 148비트신호 발생부의 출력신호를 근거로 독립제어채널에 대한 시프트 클록신호를 출력하는 출력수단을 포함하여 구성된 것을 특징으로 하는 개인통신용 단말기의 업링크시 독립제어채널 시프트 클록신호 발생장치.A personal communication system configured to form a time slot with 156.25 bits and each data bit with a length of 48 clocks based on a 13 MHz clock, comprising: clock generating means for generating a reference clock of 13 MHz; Bit synchronous signal generating means for generating a bit synchronous signal based on a clock and a frame start signal, time slot synchronous signal generating means for generating a time slot synchronous signal based on the bit synchronous signal and a reference clock, and the bit synchronous signal and a reference 148-bit signal generating means for generating a 148-bit signal based on a clock, time slot number counting means for counting the time slot synchronous signal, and outputting a current time slot number; time slot counted by the time slot number counting means A time slot strobe signal generating means for outputting a strobe signal corresponding to a first time slot on the basis of a number, the time slot number Frame synchronous signal generating means for outputting a frame synchronous signal based on the time slot number output from the counting means, frame number counting means for counting the frame synchronous signal outputted from the frame synchronous signal generating means and outputting frame number data; Latch means for storing the independent control channel number data allocated through the apparatus; reference data output means for generating predetermined reference data based on an output signal from the latch means; based on the 148-bit signal and a 0-time slot strobe signal Comparing the frame number data counted by the frame number counting means and the reference data set by the reference data output means, 148-bit signal generator and the 0-time slot output signal in a period in which both data values coincide The uplink of the individual communication terminals, characterized in that configured to include an output means for outputting the shift clock signal for the independent control channel on the basis of the output signal independently controlled channels of the shift clock signal generator. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950071090A 1995-12-31 1995-12-31 Sdcch shift clock generation device in up-link system KR0179207B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950071090A KR0179207B1 (en) 1995-12-31 1995-12-31 Sdcch shift clock generation device in up-link system

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Application Number Priority Date Filing Date Title
KR1019950071090A KR0179207B1 (en) 1995-12-31 1995-12-31 Sdcch shift clock generation device in up-link system

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KR970056047A true KR970056047A (en) 1997-07-31
KR0179207B1 KR0179207B1 (en) 1999-05-15

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