KR970055567A

KR970055567A - Phase locked loop circuit

Info

Publication number: KR970055567A
Application number: KR1019950066856A
Authority: KR
Inventors: 추우승
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-12-29
Filing date: 1995-12-29
Publication date: 1997-07-31

Abstract

전압 제어 발진기의 자주 주파수가 유지되는 범위를 벗어나는 경우에 이를 스스로 추종하게 하는 개선된 위상 동기 루프 회로가 개시된다.An improved phase locked loop circuit is disclosed that allows it to follow itself if it is outside the frequency-maintained range of the voltage controlled oscillator.

본 발명에 따른 PLL 회로는 위상 동기 루프 회로에 있어서 상기 전압 제어 발진기는 그에 인가되는 제2제어 신호에 상응하여 자주 발진 주파수가 변화하며 상기 루프 필터의 출력을 평활하여 실질적이 직류 전압을 출력하는 저역 통과 필터;상기 저역 통과 필터의 출력을 소정의 제1기준 전압과 비교하여 제1판정 신호를 출력하는 제1비교기; 상기 저역 통과 필터의 출력을 제1기준 전압보다 낮은 소정의 제2기준전압과 비교하여 제2판정 신호를 출력하는 제2비교기; 및 상기 제1비교기에서 제공되는 제1판정 신호에 응답하여 카운트업 동작을 수행하고 상기 제2비교기에서 제공되는 카운트다운 동작을 수행하며 그의 계수 출력을 상기 전압 제어발진기의 제2제어 신호로 제공하는 카운터를 포함함을 특징으로 한다.In the PLL circuit according to the present invention, in the phase locked loop circuit, the voltage controlled oscillator frequently changes in oscillation frequency corresponding to the second control signal applied thereto, and smoothes the output of the loop filter to substantially output a DC voltage. A first comparator configured to output a first determination signal by comparing an output of the low pass filter with a predetermined first reference voltage; A second comparator configured to output a second determination signal by comparing the output of the low pass filter with a predetermined second reference voltage lower than a first reference voltage; And performing a count up operation in response to the first determination signal provided by the first comparator, performing a count down operation provided by the second comparator, and providing a coefficient output thereof as a second control signal of the voltage controlled oscillator. And a counter.

본 발명에 따른 PLL회로는 VCO의 자주 주파수가 이동되었을 경우 저역 통과 필터와 2개의 비교기, 그리고 계수기를 통하여 자주 주파수를 입력 신호의 주파수에 스스로 추종하게 함으로써 외부 조정 소자가 필요없게 되는 효과가 있다.The PLL circuit according to the present invention has the effect of eliminating the need for an external adjusting element by frequently following the frequency to the frequency of the input signal through a low pass filter, two comparators, and a counter when the frequency of the VCO is shifted.

Description

Phase locked loop circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 위상 동기 루프 회로의 구성을 보인 블록도이다.3 is a block diagram showing the configuration of a phase locked loop circuit according to the present invention.

Claims

A phase comparator that generates a voltage corresponding to a phase difference between two input signals, a voltage controlled oscillator whose oscillation frequency changes according to the control voltage applied thereto, and a high frequency component generated from the phase comparator In a phase locked loop circuit having a loop filter provided as a control voltage, the voltage controlled oscillator frequently changes its oscillation frequency corresponding to the second control signal applied thereto, and smoothes the output of the loop filter to substantially reduce the direct voltage. A first comparator configured to output a first determination signal by comparing an output of the low pass filter with a predetermined first reference voltage; A second comparator configured to output a second determination signal by comparing the output of the low pass filter with a predetermined second reference voltage lower than a first reference voltage; And performing a count up operation in response to the first determination signal provided by the first comparator, and the second audio in the second comparator performs a count down operation and provides a coefficient output thereof as a second control signal of the voltage controlled oscillator. A phase-locked loop circuit.

2. The phase locked loop circuit of claim 1 wherein the voltage controlled oscillator is an emitter coupled multivibrator type oscillator each having a plurality of current sources interrupted by an output bit of the counter.

※ Note: The disclosure is based on the initial application.