KR970055494A - Input buffer circuit for semiconductor device - Google Patents

Input buffer circuit for semiconductor device Download PDF

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Publication number
KR970055494A
KR970055494A KR1019950059318A KR19950059318A KR970055494A KR 970055494 A KR970055494 A KR 970055494A KR 1019950059318 A KR1019950059318 A KR 1019950059318A KR 19950059318 A KR19950059318 A KR 19950059318A KR 970055494 A KR970055494 A KR 970055494A
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KR
South Korea
Prior art keywords
level
output
signal
buffer circuit
input buffer
Prior art date
Application number
KR1019950059318A
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Korean (ko)
Inventor
문병식
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950059318A priority Critical patent/KR970055494A/en
Publication of KR970055494A publication Critical patent/KR970055494A/en

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Abstract

본 발명은 반도체장치에서 TTL 레벨의 신호를 CMOS 레벨의 신호를 변환하는 입력 버퍼 회로의 출력 천이 속도를 개선하기 위한 것으로, 기준신호(Vref)와 입력 신호(Vin)를 비교하는 차동 증폭기(10)와, 차동 증폭기(10)의 출력을 CMOS레벨로 변환하는 제1인버터(20)와, 이 인버커(20)의 출력을 구동하는 제2인버터(30) 및, 입력 신호의 전압 레벨에 따라서 인버터(20)의 출력의 레벨 천이 속도를 빠르게 하는 부스터 회로(40)로 구성된다. 이 회로를 사용하면 반도체장치의 성능을 개선할 수 있다.The present invention is to improve the output transition speed of the input buffer circuit for converting a TTL level signal to a CMOS level signal in a semiconductor device, and the differential amplifier 10 for comparing the reference signal Vref and the input signal Vin. And a first inverter 20 for converting the output of the differential amplifier 10 to a CMOS level, a second inverter 30 for driving the output of the inverter 20, and an inverter in accordance with the voltage level of the input signal. It consists of a booster circuit 40 which speeds up the level shifting speed of the output of (20). By using this circuit, the performance of the semiconductor device can be improved.

Description

반도체장치용 입력버퍼회로Input buffer circuit for semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 입력버퍼회로의 제1실시예,2 shows a first embodiment of an input buffer circuit according to the present invention,

제3도는 본 발명에 따른 입력버퍼회로의 제2실시예,3 shows a second embodiment of an input buffer circuit according to the present invention,

제4도는 본 발명에 다른 입력버퍼회로의 제3실시예.4 is a third embodiment of an input buffer circuit according to the present invention.

Claims (4)

소정의 기준 신호와 입력 신호의 비교 결과에 따라 소정의 제1레벨의 신호 및 소정의 제2레벨의 신호를 출력하는 차동 증폭 수단과, 이 차동 증폭 수단의 출력을 상기 제1레벨 및 제2레벨에 각각 대응되는 소정의 제3 및 제4레벨의 신호로 변환하는 레벨 쉬프터 수단과, 상기 레벨 쉬프터 수단의 출력을 구동하는 구동 수단을 가지는 반도체 장치의 입력 버퍼 회로에 있어서; 상기 입력 신호의 전압 레벨에 응답하여 상기 레벨 쉬프터 수단의 출력이 상기 제3레벨 또는 상기 제4레벨로 변환되는 속도로 빠르게 하는 부스터 수단을 가지는 것을 특징으로 하는 입력 버퍼 회로.Differential amplifying means for outputting a signal of a predetermined first level and a signal of a predetermined second level according to a comparison result of a predetermined reference signal and an input signal, and outputting the output of the differential amplifying means to the first level and the second level. An input buffer circuit of a semiconductor device having a level shifter means for converting into a predetermined third and fourth level signal corresponding to the second shift signal and a driving means for driving the output of the level shifter means; And a booster means for speeding up the output of said level shifter means at a speed which is converted to said third level or said fourth level in response to a voltage level of said input signal. 제1항에 있어서, 상기 부스터 수단은, 상기 레벨 쉬프터 수단의 상기 출력이 상기 제3레벨로 변환될 때 상기 입력 신호에 응답하여 상기 레벨 쉬프터 수단의 출력 단자의 디스챠지 속도를 증가시키는 수단을 가지는 것을 특징으로 하는 입력 버퍼 회로.2. The apparatus according to claim 1, wherein said booster means has means for increasing the discharge speed of an output terminal of said level shifter means in response to said input signal when said output of said level shifter means is converted to said third level. Input buffer circuit, characterized in that. 제2항에 있어서, 상기 부스터 수단은, 상기 레벨 쉬프터 수단의 상기 출력이 상기 제4레벨로 변환될 때 상기 입력 신호에 응답하여 상기 레벨 쉬프터 수단의 출력단자의 차지-업 속도를 증가시키는 수단을 부가적으로 가지는 것을 특징으로 하는 입력 버퍼 회로.3. The apparatus according to claim 2, wherein said booster means further comprises means for increasing the charge-up speed of an output terminal of said level shifter means in response to said input signal when said output of said level shifter means is converted to said fourth level. And additionally having an input buffer circuit. 제1항 내지 제3항 붕 어느 한 항에 있어서, 상기 제1 및 제2레벨은 TTL레벨이고, 상기 제3 및 제4레벨은 CMOS 레벨인 것을 특징으로 하는 입력 버퍼 회로.4. The input buffer circuit according to any one of claims 1 to 3, wherein said first and second levels are TTL levels and said third and fourth levels are CMOS levels. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950059318A 1995-12-27 1995-12-27 Input buffer circuit for semiconductor device KR970055494A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950059318A KR970055494A (en) 1995-12-27 1995-12-27 Input buffer circuit for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950059318A KR970055494A (en) 1995-12-27 1995-12-27 Input buffer circuit for semiconductor device

Publications (1)

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KR970055494A true KR970055494A (en) 1997-07-31

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KR1019950059318A KR970055494A (en) 1995-12-27 1995-12-27 Input buffer circuit for semiconductor device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100577566B1 (en) * 2004-12-28 2006-05-08 삼성전자주식회사 Input buffer circuits
US8829969B2 (en) 2011-02-14 2014-09-09 Samsung Display Co., Ltd. Level-down shifter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100577566B1 (en) * 2004-12-28 2006-05-08 삼성전자주식회사 Input buffer circuits
US8829969B2 (en) 2011-02-14 2014-09-09 Samsung Display Co., Ltd. Level-down shifter

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