KR970054401A - Semiconductor device with triple well - Google Patents

Semiconductor device with triple well Download PDF

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Publication number
KR970054401A
KR970054401A KR1019950066024A KR19950066024A KR970054401A KR 970054401 A KR970054401 A KR 970054401A KR 1019950066024 A KR1019950066024 A KR 1019950066024A KR 19950066024 A KR19950066024 A KR 19950066024A KR 970054401 A KR970054401 A KR 970054401A
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KR
South Korea
Prior art keywords
semiconductor device
type well
triple
well region
wells
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Application number
KR1019950066024A
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Korean (ko)
Inventor
전용주
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950066024A priority Critical patent/KR970054401A/en
Publication of KR970054401A publication Critical patent/KR970054401A/en

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Abstract

본 발명은 3중 웰을 갖는 반도체 소자에 관한 것으로, 다수의 독립된 3중 웰을 구비하고, 최상부에 있는 웰을 선택적으로 각가 다른 Vbb(Back Bias)를 인가하기 위하여 한 칩내에 두개 이상의 Vbb 전압 발생 회로를 구비하고, 독립된 웰에 원하는 특성을 제조하기 위하여 독립된 웰에 각기 다른 Vbb 전압을 인가하는 반도체 소자이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having triple wells, comprising a plurality of independent triple wells, wherein two or more Vbb voltages are generated in one chip to selectively apply different Vbbs (Back Bias) to the wells at the top. A semiconductor device having a circuit and applying different Vbb voltages to independent wells in order to produce desired characteristics in separate wells.

Description

3중 웰을 갖는 반도체 소자Semiconductor device with triple well

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 기술에 의해 제조된 3중 웰을 갖는 반도체 소자를 도시한 단면도.1 is a cross-sectional view showing a semiconductor device having a triple well manufactured by a conventional technique.

제2도는 본 발명에 의해 제조된 3중 웰을 갖는 반도체 소자를 도시한 단면도.2 is a cross-sectional view showing a semiconductor device having a triple well manufactured according to the present invention.

Claims (5)

3중 웰을 갖는 반도체 소자에 있어서, 3개 이상의 독립된 웰이 구비되는 반도체 소자에서 벌트 전압 발생회로를 사용할 때 2개 이상의 Vbb 전압 발생 회로를 구비하고 Vbb 전압 발생회로에서 발생되는 각기 다른 전압을 상기 독립된 웰에 인가되도록 구비하여 특성이 다른 반도체 소자를 얻도록 하는 것을 특징으로 하는 3중 웰을 갖는 반도체 소자.A semiconductor device having a triple well, comprising two or more Vbb voltage generating circuits when using a bulk voltage generating circuit in a semiconductor device having three or more independent wells, and describing different voltages generated in the Vbb voltage generating circuit. A semiconductor device having a triple well characterized by being applied to an independent well to obtain a semiconductor device having a different characteristic. 제1항에 있어서, 상기 Vbb 전압 발생 회로는 공간에 여유가 있는 칩의 주변회로에 구비하는 것을 특징으로 하는 3중 웰을 갖는 반도체 소자.The semiconductor device according to claim 1, wherein the Vbb voltage generation circuit is provided in a peripheral circuit of a chip having a space. 3중 웰을 갖는 반도체 소자에 있어서, 반도체 기판의 일측에 구비되는 N형 웰영역과, 상기 N형 웰영역이 형성되지 않는 반도체 기판에 구비되는 다수의 P형 웰영역과, 상기 N형 웰영역 내의 소정 부분에 구비되는 다수의 P형 웰영역과 상기 N형 웰영역 내에 구비된 다수의 P형 웰영역 중에서 일정갯수는 서로 다른 Vbb 전압이 인가되도록 구비되는 다수의 Vbb 전압 발생 회로를 포함하는 것을 특징으로 하는 3중 웰을 갖는 반도체 소자.A semiconductor device having a triple well, comprising: an N-type well region provided on one side of a semiconductor substrate, a plurality of P-type well regions provided in a semiconductor substrate in which the N-type well region is not formed, and the N-type well region Among the plurality of P-type well regions provided in a predetermined portion of the plurality of P-type well region provided in the N-type well region, a predetermined number includes a plurality of Vbb voltage generating circuits provided to apply different Vbb voltage A semiconductor device having a triple well characterized by the above-mentioned. 제3항에 있어서, 상기 반도체 기판에 구비된 다수의 P형 웰영역에는 접지 전압이 인가되는 것을 특징으로 하는 3중 웰을 갖는 반도체 소자.4. The semiconductor device of claim 3, wherein a ground voltage is applied to the plurality of P-type well regions provided in the semiconductor substrate. 제3항에 있어서, 상기 P형 웰영역에 외부의 전극이 접속되도록 P형 확산영역이 구비된 것을 특징으로 하는 3중 웰을 갖는 반도체 소자.4. The semiconductor device of claim 3, wherein a P-type diffusion region is provided to connect an external electrode to the P-type well region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950066024A 1995-12-29 1995-12-29 Semiconductor device with triple well KR970054401A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950066024A KR970054401A (en) 1995-12-29 1995-12-29 Semiconductor device with triple well

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950066024A KR970054401A (en) 1995-12-29 1995-12-29 Semiconductor device with triple well

Publications (1)

Publication Number Publication Date
KR970054401A true KR970054401A (en) 1997-07-31

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Application Number Title Priority Date Filing Date
KR1019950066024A KR970054401A (en) 1995-12-29 1995-12-29 Semiconductor device with triple well

Country Status (1)

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KR (1) KR970054401A (en)

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