KR970054240A - Semiconductor Memory and Manufacturing Method - Google Patents

Semiconductor Memory and Manufacturing Method Download PDF

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KR970054240A
KR970054240A KR1019950062181A KR19950062181A KR970054240A KR 970054240 A KR970054240 A KR 970054240A KR 1019950062181 A KR1019950062181 A KR 1019950062181A KR 19950062181 A KR19950062181 A KR 19950062181A KR 970054240 A KR970054240 A KR 970054240A
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semiconductor memory
memory device
transistor
flotox
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KR1019950062181A
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KR0183794B1 (en
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한정욱
박원호
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)

Abstract

본 발명은 전기적으로 소거 및 프로그램이 가능한 반도체 기억장치 및 그 제조방법에 관한 것으로서, 특히 두 개의 다결정 실리콘 게이트를 가진 MOS트랜지스터로 구성된 FLOTOX(Floating-gate Tunneling Oxide)트랜지스터형 반도체 기억장치 및 그 제조방법에 관한 것이다. 이를 위한 본 발명은, 선택 트랜지스터와 FLOTOX 트랜지스터를 포함하여 구성되는 불휘발성 반도체 기억장치에 있어서, 상기 FLOTOX 트랜지스터의 활성 영역이 세로방향 영역부와 상기 세로방향 영역부에서 돌출분기된 가로방향 영역부로 이루어져 있으며, 상기 가로방향 영역부에서 터널산화막 영역과 채널 영역이 연결되며, 터널 윈도우영역이 상기 활성 영역 및 소정의 필드 영역에 걸쳐 형성되며, 상기 FLOTOX 트랜지스터의 게이트 영역이 상기 세로방향 영역부와 가로방향 영역부의 소정 일부분 및 상기 터널 윈도우영역의 전부를 둘러싸고 있는 것을 특징으로 한다. 이로써, 본 발명은, FLOTOX 트랜지스터의 활성 영역에 상기 FLOTOX 트랜지스터의 터널 윈도우 영역과 채널 영역이 나란히 형성되는 보조활성 영역, 즉 가로방향의 활성 영역을 부가함으로써 집적도에 따라 터널 산화막(Tunnel oxide) 영역의 크기를 자유롭게 조절할 수 있는 이점과, 셀의 읽기 동작시 터널 하부의 불순물 영역과는 무관하게 동작되도록 하여 전류 구동 능력을 향상시킬 수 있는 이점을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable and programmable semiconductor memory device and a method of manufacturing the same, and more particularly, to a FLOTOX (Floating-gate Tunneling Oxide) transistor type semiconductor memory device comprising a MOS transistor having two polycrystalline silicon gates and a method of manufacturing the same. It is about. To this end, the present invention is a nonvolatile semiconductor memory device comprising a selection transistor and a FLOTOX transistor, wherein the active region of the FLOTOX transistor comprises a vertical region portion and a horizontal region portion protruding from the vertical region portion. And a tunnel oxide region and a channel region in the horizontal region portion, a tunnel window region is formed over the active region and a predetermined field region, and a gate region of the FLOTOX transistor is in a horizontal direction with the vertical region portion. And a predetermined portion of the region portion and all of the tunnel window region. Thus, according to the present invention, by adding an auxiliary active region in which the tunnel window region and the channel region of the FLOTOX transistor are formed in parallel to the active region of the FLOTOX transistor, that is, the active region in the transverse direction, The size can be freely adjusted, and the read operation of the cell can be performed independently of the impurity region under the tunnel, thereby improving the current driving capability.

Description

반도체 기억장치 및 그 제조방법Semiconductor Memory and Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도 (a) 내지 (c)는 본 발명에 따른 FLOTOX 트랜지스터를 이용한 비휘발성 반도체 기억장치의 레이아웃도, 및 단면도.4A to 4C are layout views and cross-sectional views of a nonvolatile semiconductor memory device using the FLOTOX transistor according to the present invention.

제5도 내지 제8도는 본 발명에 따른 비휘발성 반도체 기억장치의 제조공정을 도시한 레이아웃도, 및 단면도.5 to 8 are layout views and cross-sectional views showing the manufacturing process of the nonvolatile semiconductor memory device according to the present invention.

Claims (7)

선택 트랜지스터와 FLOTOX 트랜지스터를 포함하여 구성되는 불휘발성 반도체 기억장치에 있어서, 상기 FLOTOX 트랜지스터의 활성 영역이 세로방향 영역부와 상기 세로방향 영역부에서 돌출분기된 가로방향 영역부로 이루어져 있으며, 상기 가로방향 영역부에서 터널 산화막 영역과 채널 영역이 연결되며, 터널 윈도우영역이 상기 활성 영역 및 소정의 필드 영역에 걸쳐 형성되며, 상기 FLOTOX 트랜지스터의 게이트 영역이 상기 세로방향 영역부와 가로방향 영역부의 소정 일부분 및 상기 터널 윈도우 영역의 전부를 둘러싸고 있는 것을 특징으로 하는 반도체 기억장치.In a nonvolatile semiconductor memory device comprising a selection transistor and a FLOTOX transistor, an active region of the FLOTOX transistor is composed of a vertical region portion and a horizontal region portion protruding from the vertical region portion, and the horizontal region portion. A tunnel oxide region and a channel region are connected to each other, and a tunnel window region is formed over the active region and a predetermined field region, and a gate region of the FLOTOX transistor is a predetermined portion of the vertical region portion and the horizontal region portion, and the A semiconductor memory device, which surrounds an entire tunnel window region. 제1항에 있어서, 상기 활성 영역은 "ㅏ"형태의 구조로 되어 있는 것을 특징으로 하는 반도체 기억장치.2. The semiconductor memory device according to claim 1, wherein said active region has a structure of a "ㅏ" type. 제1항에 있어서, 상기 선택 트랜지스터의 게이트는 이층의 적층구조로 되어 있는 것을 특징으로 하는 반도체 기억장치.The semiconductor memory device according to claim 1, wherein the gates of the select transistors have a stacked structure of two layers. 제1항에 있어서, 상기 선택 트랜지스터와 FLOTOX 트랜지스터 사이의 활성 영역 "」"형태로 되어 있는 것을 특징으로 하는 반도체 기억장치.The semiconductor memory device according to claim 1, wherein the semiconductor memory device is in an active region "" "between the selection transistor and the FLOTOX transistor. 선택 트랜지스터와 FLOTOX 트랜지스터를 포함하여 구성되는 불휘발성 반도체 기억장치의 제조방법에 있어서, 소정의 반도체 기판상에 가로방향 영역부과 상기 세로방향 영역부에서 돌출분기되는 가로방향 영역부로 이루어진 활성 영역을 형성하고, 국부적 산화공정을 통해 필드산화막 영역을 형성한 후, 상기 활성 영역의 중앙돌기부의 소정 부분 및 필드산화막 영역에 걸쳐 터널산화막 영역을 형성하는 단계 및 플로팅 게이트를 구성하는 일차 폴리실리콘 영역과 컨트롤 게이트를 구성하는 이차 폴리실리콘 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 기억장치의 제조방법.A method of manufacturing a nonvolatile semiconductor memory device including a selection transistor and a FLOTOX transistor, the method comprising: forming an active region including a horizontal region portion and a horizontal region portion protruding from the vertical region portion on a predetermined semiconductor substrate; Forming a field oxide region through a local oxidation process, forming a tunnel oxide region over a predetermined portion of the central projection portion and the field oxide region of the active region, and forming a primary polysilicon region and a control gate constituting the floating gate. And forming a secondary polysilicon region to constitute. 제5항에 있어서, 상기 활성 영역은 "ㅏ"형태의 구조인 것을 특징으로 하는 반도체 기억장치의 제조방법.The method of manufacturing a semiconductor memory device according to claim 5, wherein the active region has a structure of a "ㅏ" type. 제5항에 있어서, 상기 터널산화막 영역은 사진공정 및 습식 식각공정에 의해 정의되고, 이온주입공정에 의해 형성되는 것을 특징으로 하는 반도체 기억장치의 제조방법.The method of manufacturing a semiconductor memory device according to claim 5, wherein the tunnel oxide film region is defined by a photo process and a wet etching process and is formed by an ion implantation process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950062181A 1995-12-28 1995-12-28 Semiconductor memory device and its manufacturing method KR0183794B1 (en)

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