KR970054195A - SRAM Cell Manufacturing Method - Google Patents

SRAM Cell Manufacturing Method Download PDF

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Publication number
KR970054195A
KR970054195A KR1019950069455A KR19950069455A KR970054195A KR 970054195 A KR970054195 A KR 970054195A KR 1019950069455 A KR1019950069455 A KR 1019950069455A KR 19950069455 A KR19950069455 A KR 19950069455A KR 970054195 A KR970054195 A KR 970054195A
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South Korea
Prior art keywords
type
substrate
pull
junction
forming
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KR1019950069455A
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Korean (ko)
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KR100197524B1 (en
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김재갑
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김주용
현대전자산업 주식회사
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Priority to KR1019950069455A priority Critical patent/KR100197524B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 에스램 셀 제조방법을 개시한다. 개시된 본 발명은 풀-다운 트랜지스터와 풀-업 디바이스 및 억세스 트랜지스터를 구비하는 에스램 셀 제조방법에 있어서, 상기 트랜지스터의 제조방법은, 소자분리 절연막이 구비된 P형 기판상에 N형 접합 영역 예정 부위에 Vt 조절을 위한 P형의 불순물을 이온 주입하는 단계; 상기 기판의 소정 영역에 게이트 전극을 형성하는 단계; 상기 기판에 형성된 게이트 전극의 양측 기판부에 N+접합을 형성하는 단계로, 상기 예정된 N+접합 하부의 일정부분은 상기 동일 타입의 불순물에 의해 P형 불순물 농도가 증가하도록 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention discloses a method for producing an SRAM cell. Disclosed is a method for fabricating an SRAM cell having a pull-down transistor, a pull-up device, and an access transistor, wherein the method for fabricating the transistor includes an N-type junction region on a P-type substrate provided with an isolation layer. Ion implanting a P-type impurity for Vt control to the site; Forming a gate electrode in a predetermined region of the substrate; Forming N + junctions on both substrate portions of the gate electrode formed on the substrate, wherein a predetermined portion of the lower portion of the predetermined N + junction includes forming a P-type impurity concentration by the same type of impurity; It is characterized by.

Description

에스램 셀 제조방법SRAM Cell Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 풀 CMOS 에스램 셀을 나타낸 평면도.2 is a plan view showing a full CMOS SRAM cell according to the present invention.

Claims (10)

풀-다운 트랜지스터와 풀-업 디바이스 및 억세스 트랜지스터를 구비하는 에스램 셀 제조방법에 있어서, 상기 트랜지스터의 제조방법은, 소자분리 절연막이 구비된 P형 기판상에 N형 접합 영역 예정 부위에 Vt 조절을 위한 P형의 불순물을 이온 주입하는 단계; 상기 기판의 소정 영역에 게이트 전극을 형성하는 단계; 상기 기판에 형성된 게이트 전극의 양측 기판부에 N+접합을 형성하는 단계로, 상기 예정된 N+접합 하부의 일정부분은 상기 동일 타입의 불순물에 의해 P형 불순물 농도가 증가하도록 형성하는 단계를 포함하는 것을 특징으로 한는 에스램 셀 제조방법. In the method of manufacturing an S-RAM cell having a pull-down transistor, a pull-up device, and an access transistor, the method of manufacturing the transistor includes adjusting a Vt at a predetermined portion of an N-type junction region on a P-type substrate having an isolation layer. Implanting P-type impurities for the purpose of implantation; Forming a gate electrode in a predetermined region of the substrate; Forming N + junctions on both substrate portions of the gate electrode formed on the substrate, wherein a predetermined portion of the lower portion of the predetermined N + junction includes forming a P-type impurity concentration by the same type of impurity; Sram cell manufacturing method characterized in that. 제2항에 있어서, 상기 풀-업 디바이스는 폴리실리콘 저항인 것을 특징으로 하는 에스램 셀 제조방법.The method of claim 2, wherein the pull-up device is a polysilicon resistor. 제1항에 있어서, 상기 풀-업 디바이스로 P-채널 폴리실리콘 박막 트랜지스터인 것을 특징으로 하는 에스램 셀 제조방법.The method of claim 1, wherein the pull-up device is a P-channel polysilicon thin film transistor. 제1항에 있어서, 상기 풀-업 디바이스로 P-채널 벌크 모스 트랜지스터인 것을 특징으로 하는 에스램 셀 제조방법.The method of claim 1, wherein the pull-up device is a P-channel bulk MOS transistor. 제1항 내지 제4항 중 어느 한 항에 있어서, 상기 P형 불순물은 보론 또는 BF2중 선택되는 하나의 원자인 것을 특징으로 하는 에스램 셀 제조방법.5. The method of claim 1, wherein the P-type impurity is one atom selected from boron or BF 2. 6 . 제5항에 있어서, 상기 P형의 불순물의 이온 주입 조건은 5×1010내지5×1012/㎠의 농도로 이온주입하는 것을 특징으로 하는 에스램 셀 제조방법.6. The method of claim 5, wherein the ion implantation conditions of the P-type impurities are ion implanted at a concentration of 5 × 10 10 to 5 × 10 12 / cm 2. 제1항 내지 제4항 중 어느 한 항에 있어서, 상기 보론 불순물에의해 하부의 P형 불순물 농도가 증가된 N+접합이 에스램의 드라이버 트랜지스터의 N+소오스/드레인 전극의 셀 노드로 예정된 것을 특징으로 하는 에스램 셀 제조방법The N + junction according to any one of claims 1 to 4, wherein an N + junction having a lower P-type impurity concentration increased due to the boron impurity is intended as a cell node of an N + source / drain electrode of an SRAM driver transistor. SRAM cell manufacturing method characterized by 소자 분리 절연막이 형성된 N형 반도체 기판상에 게이트 채널 예정 영역에 P형 불순물을 주입하는 단계;상기 기판에 게이트 전극을 형성하는 단계; 상기 게이트 전극의 양측 기판영역에 P형 불순물 영역은 셀 노드로 예정된 P+접합 영역과 일정부분이 겹치도록 P+접합을 형성하는 단계를 포함하는 것을 특징으로 하는 에스램 셀 제조방법.Implanting a P-type impurity into a gate channel predetermined region on an N-type semiconductor substrate having an element isolation insulating film formed thereon; forming a gate electrode on the substrate; And forming a P + junction in the substrate region on both sides of the gate electrode such that the P type impurity region overlaps a predetermined portion of the P + junction region defined as a cell node. 제7항에 있어서, 상기 P형의 보론 또는 BF2중 선택되는 하나의 원자인 것을 특징으로 하는 에스램 셀 제조방법.The method of claim 7, wherein the p-type boron or BF 2 One of the atoms selected from the manufacturing method of the SRAM cell. 제7항에 있어서, 상기 P형의 불순물의 이온 주입 조건은 5×1010내지5×1012/㎠의 농도로 이온주입하는 것을 특징으로 하는 에스램 셀 제조방법.8. The method of claim 7, wherein the ion implantation conditions of the P-type impurities are ion implanted at a concentration of 5 × 10 10 to 5 × 10 12 / cm 2. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069455A 1995-12-30 1995-12-30 Fabrication method of sram cell KR100197524B1 (en)

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KR1019950069455A KR100197524B1 (en) 1995-12-30 1995-12-30 Fabrication method of sram cell

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KR100197524B1 KR100197524B1 (en) 1999-06-15

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TW522546B (en) * 2000-12-06 2003-03-01 Mitsubishi Electric Corp Semiconductor memory
KR100721958B1 (en) 2006-05-04 2007-05-25 삼성에스디아이 주식회사 Thin film transistor and method thereof

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