KR970053446A - Design rules for semiconductor devices - Google Patents

Design rules for semiconductor devices Download PDF

Info

Publication number
KR970053446A
KR970053446A KR1019950059388A KR19950059388A KR970053446A KR 970053446 A KR970053446 A KR 970053446A KR 1019950059388 A KR1019950059388 A KR 1019950059388A KR 19950059388 A KR19950059388 A KR 19950059388A KR 970053446 A KR970053446 A KR 970053446A
Authority
KR
South Korea
Prior art keywords
region
buried layer
semiconductor device
design rule
distance
Prior art date
Application number
KR1019950059388A
Other languages
Korean (ko)
Inventor
이원태
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950059388A priority Critical patent/KR970053446A/en
Publication of KR970053446A publication Critical patent/KR970053446A/en

Links

Landscapes

  • Bipolar Transistors (AREA)

Abstract

본 발명은 반도체 장치의 각 소자별 내압을 만족하는 최적의 디자인 룰을 제시하여 반도체 장치의 면적을 감소시킬 수 있는 반도체 장치의 디자인 룰에 관한 것으로, 반도체 장치의 디자인 룰은, 소자분리영역이 형성되어 있되 상기 소자분리영역내에 매립층영역이 형성되어 있고, 상기 매립층 영역상에 베이스영역을 중심으로 이미터영역과 콜렉터영역이 좌우측에 형성되어 있는 반도체기판에 있어서, 상기 매립층영역과 상기 소자분리 영역간의 제1방향의 거리가 상기 매립층영역과 상기 소자분리영역간의 제2방향의 거리에 비해 상대적으로 짧은 거리를 갖도록 형성되는 구조를 갖는다. 이와 같은 구조에 의해서, 반도체 장치의 각 소자별 내압을 만족하는 최적의 디자인 룰을 제시할 수 있고, 이에 따라 반도체 장치의 면적을 감소할 수 있다.The present invention relates to a design rule of a semiconductor device capable of reducing the area of the semiconductor device by presenting an optimal design rule that satisfies the breakdown voltage of each device of the semiconductor device. A buried layer region is formed in the device isolation region, and an emitter region and a collector region are formed on the left and right sides of the buried layer region with respect to the base region. The distance in the first direction is formed to have a relatively short distance compared to the distance in the second direction between the buried layer region and the device isolation region. With this structure, it is possible to propose an optimal design rule that satisfies the breakdown voltage of each element of the semiconductor device, thereby reducing the area of the semiconductor device.

Description

반도체 장치의 디자인 룰Design rules for semiconductor devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 실시예에 따른 반도체 장치의 디자인 룰을 보여주고 있는 레이아웃.2 is a layout showing a design rule of a semiconductor device according to an embodiment of the present invention.

Claims (4)

반도체 장치의 디자인 룰에 있어서, 소자분리영역(12)이 형성되어 있되 상기 소자분리영역(12)내에 매립층영역(22)이 형성되어 있고, 상기 매립층 영역(22)상에 베이스영역(16)을 중심으로 이미터영역(14)과 콜렉터영역(18)이 좌우측에 형성되어 있는 반도체기판(10)에 있어서, 상기 매립층영역(22)과 상기 소자분리영역(12)간의 제1방향의 거리(b')가 상기 매립층영역(22)과 상기 소자분리영역(12)간의 제2방향의 거리(a')에 비해 상대적으로 짧은 거리를 갖도록 형성되는 구조를 갖는 것을 특징으로 하는 반도체 장치의 디자인 룰.In the design rule of the semiconductor device, an isolation region 12 is formed, but a buried layer region 22 is formed in the isolation region 12, and the base region 16 is formed on the buried layer region 22. In the semiconductor substrate 10 in which the emitter region 14 and the collector region 18 are formed on the left and right sides, the distance b in the first direction between the buried layer region 22 and the device isolation region 12. ') Has a structure that is formed to have a relatively short distance compared to the distance (a') in the second direction between the buried layer region (22) and the device isolation region (12). 제1항에 있어서, 상기 제1방향은 상기 매립층영역(22)상의 콜렉터영역(18)이 형성되어 있는 방향인 것을 특징으로 하는 반도체 장치의 디자인 룰.The design rule according to claim 1, wherein the first direction is a direction in which the collector region (18) on the buried layer region (22) is formed. 제1항에 있어서, 상기 제2방향은 상기 매립층영역(22)상의 베이스영역(16)이 형성되어 있는 부위에서 상기 제1방향과 직각을 이루는 방향인 것을 특징으로 하는 반도체 장치의 디자인 룰.The semiconductor device design rule according to claim 1, wherein the second direction is a direction perpendicular to the first direction at a portion where the base region (16) on the buried layer region (22) is formed. 제1항에 있어서, 상기 제1방향의 거리는 상기 제2방향의 거리에 비해 약 10%정도의 범위내에서 짧게 형성되는 것을 특징으로 하는 반도체 장치의 디자인 룰.The design rule of claim 1, wherein the distance in the first direction is shorter than the distance in the second direction by about 10%. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950059388A 1995-12-27 1995-12-27 Design rules for semiconductor devices KR970053446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950059388A KR970053446A (en) 1995-12-27 1995-12-27 Design rules for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950059388A KR970053446A (en) 1995-12-27 1995-12-27 Design rules for semiconductor devices

Publications (1)

Publication Number Publication Date
KR970053446A true KR970053446A (en) 1997-07-31

Family

ID=66619918

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950059388A KR970053446A (en) 1995-12-27 1995-12-27 Design rules for semiconductor devices

Country Status (1)

Country Link
KR (1) KR970053446A (en)

Similar Documents

Publication Publication Date Title
KR950021600A (en) Semiconductor integrated circuit device and manufacturing method thereof
KR970072395A (en) Semiconductor devices
KR860002153A (en) Semiconductor devices
KR950007022A (en) Transistors in silicon insulators with improved source-high performance
KR970008665A (en) Patent application title: SEMICONDUCTOR DEVICE WITH ZENER DIODE FOR GATE PROTECTION
KR970024265A (en) Semiconductor devices
KR920005297A (en) Semiconductor integrated circuit device
KR980006220A (en) Semiconductor device with static electricity protection circuit
KR920005380A (en) Compound Semiconductor Device
KR970072381A (en) Structure and manufacturing method of ESD protection circuit
KR970053846A (en) Transistor of electrostatic protection circuit and manufacturing method thereof
KR910015067A (en) Semiconductor devices
KR970053446A (en) Design rules for semiconductor devices
KR980006227A (en) Semiconductor device with static electricity protection circuit
KR950020965A (en) Semiconductor devices
KR860001488A (en) Semiconductor Devices with Bipolar Transistors and IIL
KR930015106A (en) Zener diode
KR920005391A (en) Bipolar Transistor, Insulated Gate Transistor Mixed Semiconductor Device
KR910013567A (en) Semiconductor device having junction structure of heteromorphic device isolation region
KR970053793A (en) Electrostatic Discharge (ESD) Structure
KR900005561A (en) Semiconductor device
KR960019793A (en) Layout of Semiconductor Transistor and Its Semiconductor Transistor Device
KR970053873A (en) Polysilicon Resistance in Semiconductor Devices
KR960043272A (en) MOSFET and layout method
KR910010711A (en) Integrated circuit devices

Legal Events

Date Code Title Description
N231 Notification of change of applicant
WITN Withdrawal due to no request for examination