KR970049597A - Cache system to maintain complex coherency - Google Patents

Cache system to maintain complex coherency Download PDF

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Publication number
KR970049597A
KR970049597A KR1019950057084A KR19950057084A KR970049597A KR 970049597 A KR970049597 A KR 970049597A KR 1019950057084 A KR1019950057084 A KR 1019950057084A KR 19950057084 A KR19950057084 A KR 19950057084A KR 970049597 A KR970049597 A KR 970049597A
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KR
South Korea
Prior art keywords
cache
cache system
coherency
caches
write
Prior art date
Application number
KR1019950057084A
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Korean (ko)
Inventor
장성욱
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950057084A priority Critical patent/KR970049597A/en
Publication of KR970049597A publication Critical patent/KR970049597A/en

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Abstract

본 발명은 개선된 성능 및 코히어런스 유지 기능을 갖는 복합 코히어런시를 유지하는 캐쉬 시스템에 관한 것으로서, 본 발명 복합 코히어런시를 유지하는 캐쉬 시스템은 복수의 프로세서와 상기 복수의 프로세서와 주기억장치 사이에 접속되어 있는 복수의 캐쉬를 구비하여 캐쉬의 코히어런시를 유지하기 위한 자원 소모를 최소화시킬 수 있는 이점이 있다.The present invention relates to a cache system for maintaining complex coherence with improved performance and coherence maintenance. The present invention relates to a cache system for maintaining complex coherency. By providing a plurality of caches connected between the main memory device there is an advantage that can minimize the resource consumption for maintaining the coherency of the cache.

Description

복합 코히어런시를 유지하는 캐쉬 시스템Cache system to maintain complex coherency

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 실시예에 의한 복합 코히어런시를 유지하는 캐쉬 시스템의 블럭도이다.1 is a block diagram of a cache system for maintaining complex coherency according to an embodiment of the present invention.

Claims (3)

복수의 프로세서와 상기 복수의 프로세서와 주기억장치 사이에 접속되어 있는 복수의 캐쉬를 구비하는 컴퓨터 시스템에 있어서, 상기 복수의 캐쉬는 라이트-백 캐쉬와, 라이트-쓰루 캐쉬를 함께 구비하는 것을 특징으로 하는 복합 코히어런시를 유지하는 캐쉬 시스템.A computer system having a plurality of processors and a plurality of caches connected between the plurality of processors and the main memory, wherein the plurality of caches includes a write-back cache and a write-through cache. Cache system that maintains complex coherence. 제1항에 있어서, 상기 라이트-백 캐쉬는 상기 복수의 프로세서중 주 프로세서에 접속되고, 상기 라이트-쓰루 캐쉬는 그 외의 프로세서에 접속되어 있는 것을 특징으로 하는 복합 코히어런시를 유지하는 캐쉬 시스템.The cache system of claim 1, wherein the write-back cache is connected to a main processor of the plurality of processors, and the write-through cache is connected to another processor. . 제1항에 있어서, 상기 복수의 캐쉬는 더티비트가 있는 태그를 구비하는 캐쉬와 더티비트가 없는 태그를 구비하는 캐쉬인 것을 특징으로 하는 복합 코히어런시를 유지하는 캐쉬 시스템.2. The cache system of claim 1, wherein the plurality of caches are caches having a tag with dirty bits and a cache having a tag without dirty bits. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950057084A 1995-12-26 1995-12-26 Cache system to maintain complex coherency KR970049597A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950057084A KR970049597A (en) 1995-12-26 1995-12-26 Cache system to maintain complex coherency

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950057084A KR970049597A (en) 1995-12-26 1995-12-26 Cache system to maintain complex coherency

Publications (1)

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KR970049597A true KR970049597A (en) 1997-07-29

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KR1019950057084A KR970049597A (en) 1995-12-26 1995-12-26 Cache system to maintain complex coherency

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KR (1) KR970049597A (en)

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