KR970049547A - One chip micro computer - Google Patents

One chip micro computer Download PDF

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Publication number
KR970049547A
KR970049547A KR1019950047358A KR19950047358A KR970049547A KR 970049547 A KR970049547 A KR 970049547A KR 1019950047358 A KR1019950047358 A KR 1019950047358A KR 19950047358 A KR19950047358 A KR 19950047358A KR 970049547 A KR970049547 A KR 970049547A
Authority
KR
South Korea
Prior art keywords
data
unit
input
output port
program memory
Prior art date
Application number
KR1019950047358A
Other languages
Korean (ko)
Other versions
KR0165818B1 (en
Inventor
박용승
Original Assignee
문정환
Lg 반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 문정환, Lg 반도체주식회사 filed Critical 문정환
Priority to KR1019950047358A priority Critical patent/KR0165818B1/en
Publication of KR970049547A publication Critical patent/KR970049547A/en
Application granted granted Critical
Publication of KR0165818B1 publication Critical patent/KR0165818B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package

Abstract

본 발명은 원칩 마이크로 컴퓨터(One-chip Micro Computer)에 관한 것으로, 특히 프로그램 메모리부를 테스트 할 때, 프로그램 메모리 내의 데이터가 출력포트를 통하여 직접 출력되지 않도록 하여, 프로그램 메모리내의 데이터의 원치않는 유출을 방지하기에 적당하도록, 어드레스 버스 및 데이터 버스에 의해 서로 연결된 인터럽트 콘트롤러와 중앙처리장치와 데이터 메모리부와 어드레스 카운터 수단부와 프로그램 메모미부와 주변 장치부 그리고 입력/출력 포트를 포함하여 이루어지는 원칩 마이크로 컴퓨터에 있어서, 프로그램 메모리부 및 입력/출력 포트에 데이터 버스를 통하여 연결된 테스트부가 부가 형서된 것을 특징으로 하는 원칩 마이크로 컴퓨터이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcomputer. In particular, when testing a program memory unit, data in the program memory is not directly output through an output port, thereby preventing unwanted leakage of data in the program memory. One chip microcomputer comprising an interrupt controller, a central processing unit, a data memory unit, an address counter means unit, a program memo unit, a peripheral unit unit, and an input / output port, which are connected to each other by an address bus and a data bus. A test chip connected to a program memory unit and an input / output port via a data bus is additionally formatted.

Description

원칩 마이크로 컴퓨터One chip micro computer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 원칩 마이크로 컴퓨터의 실시예를 도시한 구성블럭도,3 is a block diagram showing an embodiment of a one-chip microcomputer according to the present invention;

제4도는 본 발명의 원칩 마이크로 컴퓨터 테스트 방법을 예시한 흐름도.4 is a flow chart illustrating a one-chip microcomputer test method of the present invention.

Claims (2)

어드레스 버스 및 데이터 버스에 의해 서로 연결된 인터럽트 콘트롤러와 중앙처리장치와 데이터 메모리부와 어드레스 카운터 수단부와 프로그램 메모리부와 주변장치부 그리고 입력/출력 포트를 포함하여 이루어지는 원칩 마이크로 컴퓨터에 있어서, 상기 프로그램 메모리부 및 상기 입력/출력 포트에 상기 데이터 버스를 통하여 연결된 데스트부가 부가 형성된 것을 특징으로 하는 원칩 마이크로 컴퓨터.A one-chip microcomputer comprising an interrupt controller, a central processing unit, a data memory section, an address counter means section, a program memory section, a peripheral section, and an input / output port connected to each other by an address bus and a data bus. And a test unit connected to the input / output port via the data bus. 제1항에 있어서, 상기 테스터부가 상기 프로그램 메모리부로부터 상기 데이터 버스를 통하여 데이터를 입력받는 제1저장부와, 상기 입력/출력 포트로부터 기대값을 입력받아서, 상기 제1저장부에 저장된 데이터를 비교하여 두 입력값의 동일 여부를 출력하는 비교기와, 상기 비교기의 출력을 임시저장한 후, 상기 입력/출력 포트로 전달하는 제2저장부를 포함하여 이루어지는 것을 특징으로 하는 원칩 마이크로 컴퓨터.The data storage device of claim 1, wherein the tester unit receives data from the program memory unit through the data bus, receives an expected value from the input / output port, and stores the data stored in the first storage unit. And a second storage unit configured to compare the two input values with each other and output the same, and a second storage unit configured to temporarily store the output of the comparator and transmit the temporary output to the input / output port. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950047358A 1995-12-07 1995-12-07 One chip microcomputer KR0165818B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950047358A KR0165818B1 (en) 1995-12-07 1995-12-07 One chip microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950047358A KR0165818B1 (en) 1995-12-07 1995-12-07 One chip microcomputer

Publications (2)

Publication Number Publication Date
KR970049547A true KR970049547A (en) 1997-07-29
KR0165818B1 KR0165818B1 (en) 1999-01-15

Family

ID=19438230

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950047358A KR0165818B1 (en) 1995-12-07 1995-12-07 One chip microcomputer

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KR (1) KR0165818B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100377904B1 (en) * 1999-05-11 2003-03-29 샤프 가부시키가이샤 One-chip microcomputer and control method thereof as well as an ic card having such a one-chip microcomputer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100377904B1 (en) * 1999-05-11 2003-03-29 샤프 가부시키가이샤 One-chip microcomputer and control method thereof as well as an ic card having such a one-chip microcomputer

Also Published As

Publication number Publication date
KR0165818B1 (en) 1999-01-15

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