KR970049206A - DC level shift circuit - Google Patents

DC level shift circuit Download PDF

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Publication number
KR970049206A
KR970049206A KR1019960065877A KR19960065877A KR970049206A KR 970049206 A KR970049206 A KR 970049206A KR 1019960065877 A KR1019960065877 A KR 1019960065877A KR 19960065877 A KR19960065877 A KR 19960065877A KR 970049206 A KR970049206 A KR 970049206A
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KR
South Korea
Prior art keywords
circuit
level shift
constant current
transistor
resistor
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Application number
KR1019960065877A
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Korean (ko)
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KR100214628B1 (en
Inventor
가즈히사 이와모또
Original Assignee
구자홍
Lg 전자 주식회사
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Application filed by 구자홍, Lg 전자 주식회사 filed Critical 구자홍
Publication of KR970049206A publication Critical patent/KR970049206A/en
Application granted granted Critical
Publication of KR100214628B1 publication Critical patent/KR100214628B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/72—Circuits for processing colour signals for reinsertion of DC and slowly varying components of colour signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/77—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase
    • H04N9/78—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase for separating the brightness signal or the chrominance signal from the colour television signal, e.g. using comb filter

Abstract

본 발명은, Y/C 신호 처리회로(4)에서의 휘도 신호의 직류 전위를 시프트하는 것을 목적으로 한다.An object of the present invention is to shift the DC potential of the luminance signal in the Y / C signal processing circuit 4.

문자 신호 삽입회로(5)의 직류 전위에 따라, Y/C 신호 처리회로(4)에서의 휘도 신호의 직류 전위를 시프트시키는 정전류 회로(6), 또는 커런트 미러 회로와, 정전류회로(6)의 출력을 일단 버퍼하고, 다음 단의 문자 신호 삽입회로(5)에 발생하는 불필요한 전기적 영향을 방지하는 버퍼회로(7)로 구성된다.According to the direct current potential of the character signal insertion circuit 5, the constant current circuit 6 or the current mirror circuit and the constant current circuit 6 for shifting the direct current potential of the luminance signal in the Y / C signal processing circuit 4 It consists of a buffer circuit 7 which buffers the output once and prevents unnecessary electrical influence occurring in the character signal insertion circuit 5 of the next stage.

Description

디씨(DC) 레벨 시프트회로DC level shift circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

도 2 는 본 발명에 기초한 DC 레벨 시프트회로의 제 1 실시 형태를 도시한 회로도.2 is a circuit diagram showing a first embodiment of a DC level shift circuit according to the present invention;

도 3 은 본 발명에 기초한 DC 레벨 시프트회로의 제 2 실시 형태를 도시한 회로도.3 is a circuit diagram showing a second embodiment of a DC level shift circuit based on the present invention;

Claims (4)

휘도·색신호(Y/C) 처리회로(4)와 문자 신호 삽입회로(5)와의 사이에 설치되어, 직류 전위를 재설정하기 위한 DC 레벨 시프트회로에 있어, 문자 신호 삽입회로(5)의 직류 전위에 따라, 휘도·색신호(Y/C) 처리회로(4)에서의 직류 전위를 시프트시키는 정전류 수단(1)과, 상기 정전류 수단(1)의 출력을 일단 버퍼하고, 불필요한 전기적 영향을 방지하는 완충수단(2)으로 구성되는 것을 특징으로 하는 DC 레벨 시프트회로.The DC potential of the character signal insertion circuit 5 in the DC level shift circuit provided between the luminance and color signal (Y / C) processing circuit 4 and the character signal insertion circuit 5 to reset the DC potential. According to this, the constant current means 1 for shifting the direct current potential in the luminance / color signal (Y / C) processing circuit 4 and the output of the constant current means 1 are buffered once to prevent unnecessary electrical effects. DC level shift circuit, characterized in that it comprises a means (2). 휘도·색신호 처리회로(4)와 문자 신호 삽입회로(5)와의 사이에 설치되는 DC 레벨 시프트회로이며, 영상 신호의 교류 성분을 변화시키지 않고 직류 전위를 시프트시키는 정전류 회로(1)와, 상기 정전류 회로(1)의 출력을 일단 버퍼하고, 다음 단으로 불필요한 전기적 영향을 방지하는 버퍼회로(2)로 구성되는 것을 특징으로 하는 DC 레벨 시프트 회로.A DC level shift circuit provided between the luminance and color signal processing circuit 4 and the character signal insertion circuit 5, the constant current circuit 1 shifting the DC potential without changing the AC component of the video signal, and the constant current A DC level shift circuit comprising a buffer circuit (2) which buffers the output of the circuit (1) once and prevents unnecessary electrical influences in the next stage. 제 2 항에 있어서, 상기 정전류 회로(1)는, 상기 휘도·색신호 처리회로(4)에 직렬로 접속된 제 1 저항(R1)과, 전원(Vcc)과 콜렉터의 사이에 접속된 제 2 저항(R2)과, 상기 콜렉터와 베이스를 단락하고, 에미터를 접지한 제 1 트랜지스터(TR1)와, 상기 제 1 의 트랜지스터(TR1)의 베이스에 베이스가 공통 접속되어, 콜렉터와 상기 제 1 저항이 접속된 제 2 트랜지스터(TR2)로 구성되는 것을 특징으로 하는 DC 레벨 시프트회로.3. The constant current circuit (1) according to claim 2, wherein the constant current circuit (1) includes a first resistor (R1) connected in series with the luminance and color signal processing circuit (4), and a second resistor connected between a power supply (Vcc) and a collector. A base is commonly connected to the first transistor TR1 having a short circuit between R2, the collector and the base, and the emitter grounded, and the base of the first transistor TR1, so that the collector and the first resistor are connected to each other. A DC level shift circuit comprising a connected second transistor (TR2). 제 2 항에 있어서, 상기 버퍼회로(2)는, 상기 제 1 저항(R1)과 상기 제 2의 트랜지스터(TR2)의 콜랙터 출력에 베이스를 공통 접속하고, 콜렉터를 접지한 제 3 트랜지스터(TR3)와, 상기 제 3 트랜지스터(TR3)의 에미터에 접속되어, 에미터와 제 3 의 저항(R3)의 공통 접속점을 상기 문자 신호 삽입회로(5)의 입력에 접속한 제 3 저항(R3)으로 구성되는 DC 레벨 시프트회로.The third transistor (TR3) according to claim 2, wherein the buffer circuit (2) has a base connected in common to the collector output of the first resistor (R1) and the second transistor (TR2), and the collector is grounded. ) And a third resistor R3 connected to the emitter of the third transistor TR3 and connected to a common connection point of the emitter and the third resistor R3 to the input of the character signal insertion circuit 5. DC level shift circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960065877A 1995-12-27 1996-12-14 Dc level shift circuit KR100214628B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP34160595A JP3759646B2 (en) 1995-12-27 1995-12-27 DC level shift circuit
JP341605/1995 1995-12-27

Publications (2)

Publication Number Publication Date
KR970049206A true KR970049206A (en) 1997-07-29
KR100214628B1 KR100214628B1 (en) 1999-08-02

Family

ID=18347376

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960065877A KR100214628B1 (en) 1995-12-27 1996-12-14 Dc level shift circuit

Country Status (2)

Country Link
JP (1) JP3759646B2 (en)
KR (1) KR100214628B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200111412A (en) 2019-03-19 2020-09-29 배성주 Moisture supply device of an electric rice cooker for preventing rice from drying and discoloring by supplying proper moisture
KR20200127147A (en) 2019-03-19 2020-11-10 배성주 Moisture supply device of an electric rice cooker for preventing rice from drying and discoloring by supplying proper moisture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200111412A (en) 2019-03-19 2020-09-29 배성주 Moisture supply device of an electric rice cooker for preventing rice from drying and discoloring by supplying proper moisture
KR20200127147A (en) 2019-03-19 2020-11-10 배성주 Moisture supply device of an electric rice cooker for preventing rice from drying and discoloring by supplying proper moisture

Also Published As

Publication number Publication date
JPH09187029A (en) 1997-07-15
KR100214628B1 (en) 1999-08-02
JP3759646B2 (en) 2006-03-29

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