KR970048735A - Thin-film transistor liquid crystal display module with automatic gate output adjustment according to the delay level of the gate signal - Google Patents
Thin-film transistor liquid crystal display module with automatic gate output adjustment according to the delay level of the gate signal Download PDFInfo
- Publication number
- KR970048735A KR970048735A KR1019950068227A KR19950068227A KR970048735A KR 970048735 A KR970048735 A KR 970048735A KR 1019950068227 A KR1019950068227 A KR 1019950068227A KR 19950068227 A KR19950068227 A KR 19950068227A KR 970048735 A KR970048735 A KR 970048735A
- Authority
- KR
- South Korea
- Prior art keywords
- liquid crystal
- signal
- film transistor
- gate
- transistor liquid
- Prior art date
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Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
Abstract
이 발명은 게이트 신호의 지연 정도에 따른 게이트 출력 자동조정 기능을 갖는 박막 트랜지스터 액정표시장치 모듈에 관한 것으로서, 데이타를 표시하는 박막 트랜지스터 액정 패널과; 상기 박막 트랜지스터 액정 패널의 주사선을 구동하는 게이트 구동 집적회로와; 상기 박막 트랜지스터 액정 패널의 신호선을 구동하는 데이타 구동 집적회로와; 적, 녹, 청 데이타 신호와 동기 신호를 입력받아, 상기 게이트 구동 집적회로와 상기 데이타 구동 집적회로의 타이밍을 처리하는 제어신호 처리기와; 입력전원으로 각 회로부의 동작에 필요한 전원을 공급하는 전원 발생회로와; 상기 전원 발생회로에서 발생되는 게이트 전원과 상기 박막 트랜지스터 액정 패널을 거쳐서 지연된 신호를 비교하는 비교회로와; 상기 비교회로에서의 비교가 필요한 특정 시기에만 이루어지도록 비교 시기를 결정하는 비교 시기 설정회로와; 상기 비교 시기 설정회로에서 출력되는 신호를 2비트 이상의 디지탈 신호로 변환시켜, 출력 인에이블 신호를 세팅하도록 하는 A/D 변환회로로 구성되어, 박막 트랜지스터 액정표시장치에서 각 화소를 제어하는 게이트 신호의 지연 정도를 검출하여, 출력 인에이블 신호의 자동 세팅으로 게이트 신호의 지연에 따른 게이트 출력을 조정하여 게이트 신호의 지연에 따른 화질 저하를 최소화하는 효과를 가진 게이트 신호의 지연 정도에 따른 게이트 출력 자동조정 기능을 갖는 박막 트랜지스터 액정표시장치 모듈에 관한 것이다.The present invention relates to a thin film transistor liquid crystal display module having a gate output automatic adjustment function according to a delay degree of a gate signal, comprising: a thin film transistor liquid crystal panel displaying data; A gate driving integrated circuit driving a scan line of the thin film transistor liquid crystal panel; A data driver integrated circuit driving a signal line of the thin film transistor liquid crystal panel; A control signal processor configured to receive red, green, and blue data signals and a synchronization signal, and to process timings of the gate driver integrated circuit and the data driver integrated circuit; A power generation circuit for supplying power required for the operation of each circuit portion to the input power; A comparison circuit for comparing a delayed signal through the thin film transistor liquid crystal panel with a gate power source generated in the power generation circuit; A comparison time setting circuit for determining a comparison time so as to be performed only at a specific time for which a comparison in the comparison circuit is required; A / D conversion circuit for converting the signal output from the comparison time setting circuit into a digital signal of 2 bits or more to set an output enable signal, the thin film transistor liquid crystal display device of the gate signal for controlling each pixel Detect the degree of delay and adjust the gate output according to the delay of the gate signal with automatic setting of the output enable signal to automatically adjust the gate output according to the delay of the gate signal, which has the effect of minimizing deterioration in image quality due to the delay of the gate signal. A thin film transistor liquid crystal display module having a function is provided.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제4도는 이 발명의 실시예에 따른 게이트 신호의 지연 정도에 따른 게이트 출력 자동조정 기능을 갖는 박막 트랜지스터 액정표시장치 모듈의 구성도이고,4 is a configuration diagram of a thin film transistor liquid crystal display module having a gate output automatic adjustment function according to a delay level of a gate signal according to an embodiment of the present invention.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950068227A KR0182017B1 (en) | 1995-12-30 | 1995-12-30 | Thin film transistor liquid crystal display device module having gate output automatic control function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950068227A KR0182017B1 (en) | 1995-12-30 | 1995-12-30 | Thin film transistor liquid crystal display device module having gate output automatic control function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970048735A true KR970048735A (en) | 1997-07-29 |
| KR0182017B1 KR0182017B1 (en) | 1999-05-01 |
Family
ID=19447985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950068227A KR0182017B1 (en) | 1995-12-30 | 1995-12-30 | Thin film transistor liquid crystal display device module having gate output automatic control function |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0182017B1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003162262A (en) * | 2001-11-27 | 2003-06-06 | Fujitsu Display Technologies Corp | Liquid crystal panel driving circuit and liquid crystal display device |
| KR101470627B1 (en) * | 2008-01-30 | 2014-12-08 | 엘지디스플레이 주식회사 | Display Device and Driving Method thereof |
| KR102211764B1 (en) | 2014-04-21 | 2021-02-05 | 삼성디스플레이 주식회사 | Method of driving display panel and display apparatus |
-
1995
- 1995-12-30 KR KR1019950068227A patent/KR0182017B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR0182017B1 (en) | 1999-05-01 |
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| E701 | Decision to grant or registration of patent right | ||
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| FPAY | Annual fee payment |
Payment date: 20071127 Year of fee payment: 10 |
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| LAPS | Lapse due to unpaid annual fee |