KR970029866A - Elimination detecting method using reference cell of non-volatile semiconductor memory - Google Patents

Elimination detecting method using reference cell of non-volatile semiconductor memory Download PDF

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Publication number
KR970029866A
KR970029866A KR1019950039921A KR19950039921A KR970029866A KR 970029866 A KR970029866 A KR 970029866A KR 1019950039921 A KR1019950039921 A KR 1019950039921A KR 19950039921 A KR19950039921 A KR 19950039921A KR 970029866 A KR970029866 A KR 970029866A
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South Korea
Prior art keywords
memory
reference voltage
bit line
cell
semiconductor memory
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KR1019950039921A
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Korean (ko)
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KR0172364B1 (en
Inventor
이동기
김명재
최병순
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김광호
삼성전자 주식회사
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Publication of KR970029866A publication Critical patent/KR970029866A/en
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Publication of KR0172364B1 publication Critical patent/KR0172364B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits

Abstract

1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

불 휘발성 반도체 메모리Nonvolatile Semiconductor Memory

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

접힘비트라인 구조의 메모리에서 개선된 소거검증 방법을 제공한다.An improved erase verification method in a memory of a folded bit line structure is provided.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

다수의 메모리 트랜지스터들이 하나의 낸드셀 스트링을 구성하며, 상기 메모리 트랜지스터들은 행 방향의 워드라인과 열방향의 비트라인에 매트릭스형태로 배열되어 메모리 셀 어레이를 형성하고, 상기 비트라인은 접힘 비트라인 구조를 가지며, 상기 비트라인에 기준전압을 제공하기 위해 선택 트랜지스터 및 기준 셀을 가지는 불 휘발성 반도체 메모리의 소거검증 방법은: 상기 메모리 셀 어레이내의 메모리 트랜지스터가 소거된 후, 미리 설정된 제1,2기준전압중 제2기준전압을 상기 기준셀의 제어 게이트에 인가하는 단계와: 상기 소거된 메모리 트랜지스터에 연결된 상기 비트라인의 전압레벨을 상기 제2기준전압과 비교하는 단계와; 상기 비트라인의 전압레벨이 상기 제2기준전압 이하인 경우에 검증을 완료하는 단계를 가진다.A plurality of memory transistors constitute a single NAND cell string, and the memory transistors are arranged in a matrix form on word lines in a row direction and bit lines in a column direction to form a memory cell array, and the bit lines have a folded bit line structure. An erase verification method of a nonvolatile semiconductor memory having a selection transistor and a reference cell to provide a reference voltage to the bit line includes: first and second reference voltages set after the memory transistors in the memory cell array are erased; Applying a second reference voltage to a control gate of the reference cell, comparing the voltage level of the bit line connected to the erased memory transistor with the second reference voltage; Verifying when the voltage level of the bit line is less than or equal to the second reference voltage.

4. 발명의 중요한 용도4. Important uses of the invention

불 휘발성 반도체 메모리의 소거검증에 적합하게 사용된다.It is suitably used for erasure verification of nonvolatile semiconductor memory.

Description

불휘발성 반도체 메모리의 기준셀을 이용한 소거검증 방법Erasing Verification Method Using Reference Cell of Nonvolatile Semiconductor Memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 반도체 메모리의 회로도.3 is a circuit diagram of a semiconductor memory according to the present invention.

Claims (4)

다수의 메모리 트랜지스터들이 하나의 낸드셀 스트링을 구성하며, 상기 메모리 트랜지스터들은 행 방향의 워드라인과 열방향의 비트라인에 매트릭스형태로 배열되어 메모리 셀 어레이를 형성하고, 상기 비트라인은 접힘 비트라인 구조를 가지며, 상기 비트라인에 기준전압을 제공하기 위해 선택 트랜지스터 및 기준 셀을 가지는불 휘발성 반도체 메모리의 소거검증 방법에 있어서: 상기 메모리 셀 어레이내의 메모리 트랜지스터가 소거된 후, 미리 설정된 제1,2기준전압중 제2기준전압을 상기 기준셀의 제어 게이트에 인가하는 단계와: 상기 소거된 메모리 트랜지스터에 연결된 상기 비트라인의 전압레벨을 상기 제2기준압과 비교하는 단계와: 상기 비트라인의 전압레벨이 상기 제2기준전압 이하인 경우에 검증을 완료하는 단계를 가짐을 특징으로 하는 방법.A plurality of memory transistors constitute a single NAND cell string, and the memory transistors are arranged in a matrix form on word lines in a row direction and bit lines in a column direction to form a memory cell array, and the bit lines have a folded bit line structure. A method of erasing and verifying a nonvolatile semiconductor memory having a select transistor and a reference cell to provide a reference voltage to the bit line, the method comprising: after the memory transistor in the memory cell array is erased Applying a second reference voltage among the voltages to a control gate of the reference cell, comparing the voltage level of the bit line connected to the erased memory transistor with the second reference voltage: And if the verification is equal to or less than the second reference voltage, completing the verification. Way. 제1항에 있어서, 상기 제2기준전압은 상기 제1기준전압 보다 높은 전압임을 특징으로 하는 방법.The method of claim 1, wherein the second reference voltage is higher than the first reference voltage. 제1항에 있어서, 상기 제1기준전압은 노말 리드시에 상기 기준셀의 제어 게이트에 제공되는 것을 특징으로 하는 방법.The method of claim 1, wherein the first reference voltage is provided to the control gate of the reference cell at the time of normal reading. 접힘구조의 비트라인에 기준전압을 제공하기 위해 선택 트랜지스터 및 기준 셀 및 메모리 셀 어레이를 가지는 불 휘발성 반도체 메모리의 구동방법에 있어서: 상기 메모리 셀 어레이내의 메모리 트랜지스터가 소거된 후, 소거검증시에 미리 설정된 제1,2기준전압중 제2기준전압을 상기 기준셀의 제어 게이트에 인가하여 소거된 메모리 셀에 대한 검증을 수행하고, 노말 리드시에는 상기 제1기준전압을 상기 기준셀의 제어 게이트 인가하여 셀싱마진을 높이는 것을 특징으로 하는 방법.A method of driving a nonvolatile semiconductor memory having a selection transistor, a reference cell, and a memory cell array to provide a reference voltage to a bit line of a folded structure, the method comprising: erasing a memory transistor in the memory cell array in advance after erasing verification The second reference voltage among the set first and second reference voltages is applied to the control gate of the reference cell to perform verification on the erased memory cell, and during normal reading, the first reference voltage is applied to the control gate of the reference cell. To increase the selling margin.
KR1019950039921A 1995-11-06 1995-11-06 Elimination detecting method using reference cell of non-volatile semiconductor memory KR0172364B1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6538922B1 (en) 2000-09-27 2003-03-25 Sandisk Corporation Writable tracking cells
KR100470574B1 (en) * 2000-12-11 2005-03-08 가부시끼가이샤 도시바 Non-volatile semiconductor memory device
US7237074B2 (en) 2003-06-13 2007-06-26 Sandisk Corporation Tracking cells for a memory system
US7301807B2 (en) 2003-10-23 2007-11-27 Sandisk Corporation Writable tracking cells

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6538922B1 (en) 2000-09-27 2003-03-25 Sandisk Corporation Writable tracking cells
US6714449B2 (en) 2000-09-27 2004-03-30 Sandisk Corporation Sense amplifier suitable for analogue voltage levels
US6873549B2 (en) 2000-09-27 2005-03-29 Sandisk Corporation Writable tracking cells
KR100470574B1 (en) * 2000-12-11 2005-03-08 가부시끼가이샤 도시바 Non-volatile semiconductor memory device
US7237074B2 (en) 2003-06-13 2007-06-26 Sandisk Corporation Tracking cells for a memory system
US7916552B2 (en) 2003-06-13 2011-03-29 Sandisk Corporation Tracking cells for a memory system
US8072817B2 (en) 2003-06-13 2011-12-06 Sandisk Technologies Inc. Tracking cells for a memory system
US7301807B2 (en) 2003-10-23 2007-11-27 Sandisk Corporation Writable tracking cells

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