KR970029860A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR970029860A
KR970029860A KR1019950044898A KR19950044898A KR970029860A KR 970029860 A KR970029860 A KR 970029860A KR 1019950044898 A KR1019950044898 A KR 1019950044898A KR 19950044898 A KR19950044898 A KR 19950044898A KR 970029860 A KR970029860 A KR 970029860A
Authority
KR
South Korea
Prior art keywords
data
cell array
memory cell
chip enable
enable signal
Prior art date
Application number
KR1019950044898A
Other languages
Korean (ko)
Other versions
KR100200689B1 (en
Inventor
장철응
조성희
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950044898A priority Critical patent/KR100200689B1/en
Publication of KR970029860A publication Critical patent/KR970029860A/en
Application granted granted Critical
Publication of KR100200689B1 publication Critical patent/KR100200689B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)

Abstract

본 발명은 반도체 메모리 장치에 관해 게시한다. 종래에는 시간이 짧은 특정시구간에서 비트라인과 더미비트라인이 충분히 프리차지되지 않은 상태에서 시구간이 전환될 경우, 감응증폭기가 메모리셀어레이에 저장된 데이터를 틀리게 감지할 수가 있었다. 그러나 본 발명은 칩인에이블신호와 주소신호에 의해 제어되며 전원을 제공하는 펄스제어부와, 데이터를 저장하고 저장된 데이터를 독출하기 위해 상기 칩인에이블신호와 주소신호에 의해 그 주소가 지정되는 메모리셀어레이와, 상기 펄스제어부에 의해 제어되는 감응증폭기 및 데이타래취제어부와, 상기 감응즉폭기 및 데이터래취제어부에 의해 상기 메모리셀어레이의 데이터를 감지하는 감응증폭기 및 데이터래취블록을 갖는 반도체 메모리 장치에 있어서, 상기 감응증폭기 및 데이타래취블록은 상기 칩인에이블 신호에 연결하도록 구성함으로서 시간구간의 장단에 관계없이 메모리셀어레이에 저장된 데이터를 정확하게 감지할 수가 있다.The present invention relates to a semiconductor memory device. Conventionally, when a time period is switched in a state in which a bit line and a dummy bit line are not sufficiently precharged in a short time period, a sensitive amplifier could incorrectly sense data stored in a memory cell array. However, the present invention provides a pulse control unit which is controlled by a chip enable signal and an address signal and provides power, a memory cell array whose address is designated by the chip enable signal and an address signal for storing data and reading stored data. And a sensitive amplifier and a data latch control controlled by the pulse controller, and a sensitive amplifier and a data latch block for sensing data of the memory cell array by the sensitive immediate amplifier and data latch control. The sensitive amplifier and data latch block can be connected to the chip enable signal so that the data stored in the memory cell array can be accurately detected regardless of the length of time.

Description

반도체 메모리 장치Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의한 반도체 메모리 장치의 개략적인 블록도.3 is a schematic block diagram of a semiconductor memory device according to the present invention.

Claims (2)

칩인에이블신호와 주소신호에 의해 제어되는 주소전이검출부와, 전원을 제공하는 전원검출부와, 데이터를 저장하고 저장된 데이터는 상기 주소신호에 의해 제어되는 메모리셀어레이와, 상기 주소전이검출부와 전원검출부에 의해 제어되는 감응증폭기 및 데이터래취제어부와, 상기 감응증폭기 및 데이터래취제어부와 주소전이검출부에 의해 상기 메모리셀어레이의 데이터를 독출하는 감응증폭기 및 데이터래취부를 갖는 반도체 메모리 장치에 있어서, 상기 감응증폭기 및 데이터래취부는 상기 칩인에이블신호에도 연결되는 것을 특징으로 하는 반도체 메모리 장치.An address transition detection unit controlled by a chip enable signal and an address signal, a power detection unit providing power, a memory cell array storing data and stored data, the address transition detection unit and a power detection unit A semiconductor memory device having an induction amplifier and a data latch control unit controlled by a control unit; And an amplifier and a data latching unit are also connected to the chip enable signal. 제1항에 있어서, 상기 전원검출부는 지연회로를 더 구비하는 것을 특징으로 하는 반도체 메모리 장치.The semiconductor memory device of claim 1, wherein the power detector further comprises a delay circuit.
KR1019950044898A 1995-11-29 1995-11-29 Semiconductor memory device KR100200689B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950044898A KR100200689B1 (en) 1995-11-29 1995-11-29 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950044898A KR100200689B1 (en) 1995-11-29 1995-11-29 Semiconductor memory device

Publications (2)

Publication Number Publication Date
KR970029860A true KR970029860A (en) 1997-06-26
KR100200689B1 KR100200689B1 (en) 1999-06-15

Family

ID=19436536

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950044898A KR100200689B1 (en) 1995-11-29 1995-11-29 Semiconductor memory device

Country Status (1)

Country Link
KR (1) KR100200689B1 (en)

Also Published As

Publication number Publication date
KR100200689B1 (en) 1999-06-15

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