KR970029778A - Bitline Precharge Circuit - Google Patents

Bitline Precharge Circuit Download PDF

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Publication number
KR970029778A
KR970029778A KR1019950040048A KR19950040048A KR970029778A KR 970029778 A KR970029778 A KR 970029778A KR 1019950040048 A KR1019950040048 A KR 1019950040048A KR 19950040048 A KR19950040048 A KR 19950040048A KR 970029778 A KR970029778 A KR 970029778A
Authority
KR
South Korea
Prior art keywords
bias
cell
signal
bit line
data
Prior art date
Application number
KR1019950040048A
Other languages
Korean (ko)
Other versions
KR100206868B1 (en
Inventor
박규하
Original Assignee
문정환
Lg 반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, Lg 반도체주식회사 filed Critical 문정환
Priority to KR1019950040048A priority Critical patent/KR100206868B1/en
Publication of KR970029778A publication Critical patent/KR970029778A/en
Application granted granted Critical
Publication of KR100206868B1 publication Critical patent/KR100206868B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

본 발명은 비트라인 프리챠지 회로에 관한 것으로, 종래 기술은 임의의 셀을 엑세스할 때 다음 싸이클에 엑세스될 셀이 온되어 다음 싸이클에 선택될 비트 라인과 접지간에 경로가 형성되어 방전되므로 다음 싸이클에서 비트 라인이 하이 레벨로 충분히 상승하지 못하여 데이타 인식 시간이 지연되거나 하이 데이타가 로우 데이타로 인식되는 오동작의 문제점이 있었다. 이러한 문제점을 개선하기 위하여 본 발명은 셀의 데이타를 감지한 후 센스 앰프를 모두 오프시키고 모든 선택 라인을 오프시킨 상태에서 비트라인을 프리 챠지시키도록 창안한 것으로, 본 발명은 데이타의 감지가 종료되면 비트 라인을 프리챠지시키므로 다음 싸이클에서 비트 라인의 레벨이 충분히 상승하여 셀의 저장 데이타를 정확히 감지할 수 있음은 물론 고속 동작이 가능한 효과가 있다.The present invention relates to a bit line precharge circuit. In the prior cycle, when a cell is accessed, a cell to be accessed in the next cycle is turned on, and a path is formed and discharged between the bit line to be selected in the next cycle and ground. There has been a problem of a malfunction in which the data recognition time is delayed because the bit line does not sufficiently rise to the high level or the high data is recognized as the low data. In order to solve this problem, the present invention has been devised to precharge the bit line with the sense amplifiers turned off and all the select lines off after sensing the data of the cell. By precharging the bit line, the level of the bit line is sufficiently increased in the next cycle, so that the stored data of the cell can be accurately detected, and high speed operation can be performed.

Description

비트라인 프리챠지 회로Bitline Precharge Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 비트라인 프리챠지 회로의 블럭도.2 is a block diagram of a bit line precharge circuit of the present invention.

제3도는 제2도의 동작 타이밍도.3 is an operation timing diagram of FIG.

제4도는 본 발명의 적용 여부에 따른 예시 파형도.4 is an exemplary waveform diagram according to the application of the present invention.

Claims (3)

데이타를 저장하는 복수개의 셀 체인과, 셀렉트라인 선택신호(Xs)와 워드라인 선택 신호(WLi-i=0∼n)를 상기 복수개의 셀 체인에 출력하는 X-디코더와, Y-어드레스(Yi, i=0∼m)에 따라 상기 셀 체인의 저장데이타를 감지하여 센스 앰프로 출력하는 열선택 스위치와, 바이어스 신호(BIAS-EN)에 의해 프리챠지 전압(VB)을 출력하는 프리챠지 수단과, 바이어스 신호(BIAS-EN)를 반전함에 의해 상기 프리챠지 수단의 출력(VB)을 상기 셀 체인에 출력하는 바이어스 게이트부(205)로 구성한 비트라인 프리챠지 회로.A plurality of cell chains storing data, an X-decoder for outputting a select line selection signal Xs and a word line selection signal WLi-i = 0 to n to the plurality of cell chains, and a Y-address (Yi) , i = 0 to m), a column select switch for sensing stored data of the cell chain and outputting the sensed data to a sense amplifier, and precharge means for outputting a precharge voltage V B by a bias signal BIAS-EN. And a bias gate portion (205) for outputting the output (V B ) of the precharge means to the cell chain by inverting a bias signal (BIAS-EN). 제1항에 있어서, X-디코더는 데이타 감지 구간에서 셀렉트라인 선택신호(Xs)는 하이, 워드라인 선택신호(WL)는 로우로 출력하고 프리챠지 구간에서 셀렉트라인 선택신호(Xs)는 로우, 워드라인 선택신호(WL)는 하이로 출력하도록 구성한 것을 특징으로 하는 비트라인 프리챠지 회로.The method of claim 1, wherein the X-decoder outputs the select line select signal Xs high in the data sensing period, the word line select signal WL low, and the select line select signal Xs low in the precharge period. And a word line select signal (WL) is configured to output high. 제1항에 있어서, 바이어스 게이트 수단은 바이어스 신호(BIAS-EN)를 반전시키는 인버터와, 이 인버터의 출력에 턴온, 턴오프되어 프리챠지 수단과 셀 체인을 접속시키는 N개의 모스 트랜지스터로 구성한 것을 특징으로 하는 비트라인 프리챠지 회로.2. The bias gate device according to claim 1, wherein the bias gate means comprises an inverter for inverting the bias signal BIAS-EN, and N MOS transistors for turning on and off the output of the inverter to connect the precharge means and the cell chain. Bit line precharge circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950040048A 1995-11-07 1995-11-07 Bit line precharge circuit KR100206868B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950040048A KR100206868B1 (en) 1995-11-07 1995-11-07 Bit line precharge circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950040048A KR100206868B1 (en) 1995-11-07 1995-11-07 Bit line precharge circuit

Publications (2)

Publication Number Publication Date
KR970029778A true KR970029778A (en) 1997-06-26
KR100206868B1 KR100206868B1 (en) 1999-07-01

Family

ID=19433209

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950040048A KR100206868B1 (en) 1995-11-07 1995-11-07 Bit line precharge circuit

Country Status (1)

Country Link
KR (1) KR100206868B1 (en)

Also Published As

Publication number Publication date
KR100206868B1 (en) 1999-07-01

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