KR970024621A - Video encoder - Google Patents

Video encoder Download PDF

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Publication number
KR970024621A
KR970024621A KR1019950036887A KR19950036887A KR970024621A KR 970024621 A KR970024621 A KR 970024621A KR 1019950036887 A KR1019950036887 A KR 1019950036887A KR 19950036887 A KR19950036887 A KR 19950036887A KR 970024621 A KR970024621 A KR 970024621A
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KR
South Korea
Prior art keywords
transistors
buffer
pmos
pmos transistors
electrode connected
Prior art date
Application number
KR1019950036887A
Other languages
Korean (ko)
Other versions
KR0153045B1 (en
Inventor
김정철
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950036887A priority Critical patent/KR0153045B1/en
Publication of KR970024621A publication Critical patent/KR970024621A/en
Application granted granted Critical
Publication of KR0153045B1 publication Critical patent/KR0153045B1/en

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1431—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using a single graphics controller
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/04—Display device controller operating with a plurality of display units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Graphics (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Analogue/Digital Conversion (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Picture Signal Circuits (AREA)
  • Amplifiers (AREA)

Abstract

본 발명은 비데오 엔코더를 공개한다. 그 회로는 입력신호를 위한 기준전압이 입력되는 포지티브 입력단자를 가진 버퍼, 상기 버퍼의 네거티브 입력단자와 접지전압사이에 연결된 기준저항, 상기 버퍼의 출력단자에 연결된 게이트 전극과 상기 버퍼의 네거티 입력단자에 연결된 소오스 전국을 가진 NMOS트랜지스터, 전원전압이 인가되는 소오스 전극과 상기 NMOS트랜지스터의 드레인 전국에 연결된 게이트 전극을 가진 복수개의 제1PMOS트랜지스터들, 상기 복수개의 제1PMOS트랜지스터들의 드레인 전극들사이에 연결된 제2PMOS트랜지스터들, 상기 PMOS트랜지스터들을 제어하기 위한 제어수단, 및 상기 전원전압에 연결된 소오스 전극과 상기 복수개의 제1PM0S트랜지스터들의 게이트 전극에 연결된 게이트 전극을 가지고 상기 복수개의 제1PM0S트랜지스터들의 크기들을 합한 값의 크기를 가지는 제3PMOS트랜지스터로 구성되어 있다. 따라서, 전루의 소모없이 복수개의 모니터를 구동할 수 있다.The present invention discloses a video encoder. The circuit includes a buffer having a positive input terminal to which a reference voltage for an input signal is input, a reference resistor connected between the negative input terminal of the buffer and a ground voltage, a gate electrode connected to the output terminal of the buffer, and a negative input of the buffer. An NMOS transistor having a source nation connected to a terminal, a source electrode to which a power supply voltage is applied, a plurality of first PMOS transistors having a gate electrode connected to a drain nation of the NMOS transistor, and connected to drain electrodes of the plurality of first PMOS transistors The sum of the sizes of the plurality of first PM0S transistors includes second PMOS transistors, control means for controlling the PMOS transistors, a source electrode connected to the power supply voltage, and a gate electrode connected to gate electrodes of the plurality of first PM0S transistors. Third PMOS having a size of It is composed of transistors. Therefore, it is possible to drive a plurality of monitors without exhausting the current.

Description

비데오 엔코더Video encoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 비데오 엔코더의 회로도이다.2 is a circuit diagram of the video encoder of the present invention.

Claims (5)

기준전압이 입력되는 포지티브 입력단자를 가진 버퍼 ; 상기 버퍼의 네거티브 입력단자와 접지전압사이에 연결된 기준저항 ; 상기 버퍼의 출력단자에 연결된 게이트 전극과 산기 버퍼의 네거티브 입력단자에 연결된 소오스 전극을 가진 NMOS트랜지스터 ; 전원전압이 인가되는 소오스 전극과 상기 NMOS트랜지스터의 드레인 전극에 연결된 게이트 전극을 가진 복수개의 제1PMOS트랜지스터들 ; 상기 복수개의 제1PMOS트랜지스터들의 드레인 전극들 사이에 연결된 제2PMOS트랜지스터들을 제어하기 위한 제어수단 ; 및 상기 전원전압에 연결된 소오스 전극과 상기 복수개의 제1PMOS트랜지스터들의 게이트 전극에 연결된 게이트 전극을 가지고 상기 복수개의 제1PMOS트랜지스터들의 크기들을 합한 값의 크기를 가지는 제3PMOS트랜지스터를 구비한 것을 특징으로 하는 비데오 엔코더.A buffer having a positive input terminal to which a reference voltage is input; A reference resistor connected between the negative input terminal of the buffer and a ground voltage; An NMOS transistor having a gate electrode connected to the output terminal of the buffer and a source electrode connected to the negative input terminal of an acid buffer; A plurality of first PMOS transistors having a source electrode to which a power supply voltage is applied and a gate electrode connected to the drain electrode of the NMOS transistor; Control means for controlling second PMOS transistors connected between drain electrodes of the plurality of first PMOS transistors; And a third PMOS transistor having a source electrode connected to the power supply voltage and a gate electrode connected to the gate electrodes of the plurality of first PMOS transistors, the third PMOS transistor having a magnitude of the sum of the sizes of the plurality of first PMOS transistors. Encoder. 제1항에 있어서, 상기 복수개의 제1PMOS트랜지스터들의 각각은 크기가 다른 것을 특징으로 하는 비데오 엔코더.The video encoder of claim 1, wherein each of the plurality of first PMOS transistors has a different size. 기준전압을 버퍼하기 위한 버퍼 ; 상기 버퍼의 출력신호에 의해서 인에이블되는 인에이블 트랜지스터 ; 전원전압과 상기 인에이블 트랜지스터사이에 병렬로 연결된 복수개의 제1트랜지스터들 ; 상기 복수개의 제1트랜지스터들사이에 연결되어 상기 인에이블 트랜지스터로 흐르는 전류를 제어하기 위한 복수개의 스위칭 트랜지스터들 ; 상기 복수개의 스위칭 트랜지스터들을 제어하기 위한 제어수단 ; 및 상기 인에이블 트랜지스터를 통하여 흐르는 전류를 미러하고 상기 복수개의 제1트랜지스터들의 크기를 합한 값과 동일한 크기를 가지는 제2트랜지스터를 구비한 것을 특징으로 하는 비데오 엔코더.A buffer for buffering the reference voltage; An enable transistor enabled by an output signal of the buffer; A plurality of first transistors connected in parallel between a power supply voltage and the enable transistor; A plurality of switching transistors connected between the plurality of first transistors for controlling a current flowing to the enable transistor; Control means for controlling the plurality of switching transistors; And a second transistor mirroring a current flowing through the enable transistor and having a size equal to a sum of the sizes of the plurality of first transistors. 제3항에 있어서, 상기 제1,2트랜지스터들은 PMOS트랜지스터들인 것을 특징으로 하는 비데오 엔코더.4. The video encoder of claim 3, wherein the first and second transistors are PMOS transistors. 제3항에 있어서, 상기 복수개의 제1트랜지스터들의 각각은 크기가 다른 것을 특징으로 하는 비데오 엔코더.The video encoder of claim 3, wherein each of the plurality of first transistors has a different size. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950036887A 1995-10-24 1995-10-24 Video encoder KR0153045B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950036887A KR0153045B1 (en) 1995-10-24 1995-10-24 Video encoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950036887A KR0153045B1 (en) 1995-10-24 1995-10-24 Video encoder

Publications (2)

Publication Number Publication Date
KR970024621A true KR970024621A (en) 1997-05-30
KR0153045B1 KR0153045B1 (en) 1998-12-15

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KR1019950036887A KR0153045B1 (en) 1995-10-24 1995-10-24 Video encoder

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KR0153045B1 (en) 1998-12-15

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