KR970024546A - Delay circuit - Google Patents

Delay circuit Download PDF

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Publication number
KR970024546A
KR970024546A KR1019950034101A KR19950034101A KR970024546A KR 970024546 A KR970024546 A KR 970024546A KR 1019950034101 A KR1019950034101 A KR 1019950034101A KR 19950034101 A KR19950034101 A KR 19950034101A KR 970024546 A KR970024546 A KR 970024546A
Authority
KR
South Korea
Prior art keywords
constant voltage
delay circuit
mos transistor
circuit
capacitor
Prior art date
Application number
KR1019950034101A
Other languages
Korean (ko)
Other versions
KR0177398B1 (en
Inventor
김호현
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950034101A priority Critical patent/KR0177398B1/en
Publication of KR970024546A publication Critical patent/KR970024546A/en
Application granted granted Critical
Publication of KR0177398B1 publication Critical patent/KR0177398B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load

Abstract

본 발명은 모스 트랜지스터와 캐패시터를 구비하는 딜레이 회로에 있어서, 전원전압이 입력되어 출력된 정전압이 모스 트랜지스터의 일 채널전극에 입력되어서, 모스 트랜지스터가 정전압에 의해 동작되도록 하는 정전압회로를 부가하는 것을 특징으로 한다.The present invention provides a delay circuit including a MOS transistor and a capacitor, wherein a constant voltage inputted with a power supply voltage is input to one channel electrode of the MOS transistor, so that a constant voltage circuit is added so that the MOS transistor is operated by a constant voltage. It is done.

Description

딜레이(delay) 회로Delay circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 딜레이 회로의 일실시예를 도시한 회로도.2 is a circuit diagram showing an embodiment of a delay circuit according to the present invention.

Claims (2)

모스 트랜지스터와 캐패시터를 구비하는 딜레이 회로에 있어서, 전원전압이 입력되어 출력된 정전압이 상기 모스 트랜지스터의 일 채널전극에 입력되어서, 상기 모스 트랜지스터가 정전압에 의해 동작되도록 하는 정전압회로를 부가하는 것을 특징으로 하는 딜레이 회로.A delay circuit comprising a MOS transistor and a capacitor, wherein the constant voltage inputted and outputted by a power supply voltage is input to one channel electrode of the MOS transistor, so that a constant voltage circuit is added so that the MOS transistor is operated by a constant voltage. Delay circuit. 제1항에 있어서, 피모스 트랜지스터와 엔모스 트랜지스터로서 다 수의 인버터부와, 상기 인버터부의 사이에 병렬접속되는 캐패시터로 이루어지되, 상기 피모스 트랜지스터의 소오스 전극에 상기 정전압회로의 출력인 정전압이 인가되도록 하는 것을 특징으로 하는 딜레이 회로.2. The PMOS transistor and the NMOS transistor according to claim 1, comprising a plurality of inverter parts and a capacitor connected in parallel between the inverter parts, wherein a constant voltage which is an output of the constant voltage circuit is applied to a source electrode of the PMOS transistor. Delay circuit characterized in that it is applied. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950034101A 1995-10-05 1995-10-05 Delay circuit KR0177398B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950034101A KR0177398B1 (en) 1995-10-05 1995-10-05 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950034101A KR0177398B1 (en) 1995-10-05 1995-10-05 Delay circuit

Publications (2)

Publication Number Publication Date
KR970024546A true KR970024546A (en) 1997-05-30
KR0177398B1 KR0177398B1 (en) 1999-04-01

Family

ID=19429320

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950034101A KR0177398B1 (en) 1995-10-05 1995-10-05 Delay circuit

Country Status (1)

Country Link
KR (1) KR0177398B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102426011B1 (en) 2020-12-30 2022-07-29 사단법인대기환경모델링센터 Stand-alone carbon analysis multi unit

Also Published As

Publication number Publication date
KR0177398B1 (en) 1999-04-01

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