KR970023951A - EM test pattern of metallization layer in semiconductor device - Google Patents

EM test pattern of metallization layer in semiconductor device Download PDF

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Publication number
KR970023951A
KR970023951A KR1019950038992A KR19950038992A KR970023951A KR 970023951 A KR970023951 A KR 970023951A KR 1019950038992 A KR1019950038992 A KR 1019950038992A KR 19950038992 A KR19950038992 A KR 19950038992A KR 970023951 A KR970023951 A KR 970023951A
Authority
KR
South Korea
Prior art keywords
semiconductor device
test pattern
metal
metal interconnection
metallization layer
Prior art date
Application number
KR1019950038992A
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Korean (ko)
Inventor
유현기
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950038992A priority Critical patent/KR970023951A/en
Publication of KR970023951A publication Critical patent/KR970023951A/en

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Abstract

반도체장치의 금속배선층의 EM 테스트 패턴이 개시되어 있다. 본 발명은 반도체장치의 테스트 패턴에 있어서, 실제의 반도체장치와 동일한 표면요철을 갖는 반도체기판 상에 서로 최소 디자인 룰에 의한 간격을 유지하면서 배치된 복수의 제1 금속배선; 및 상기 복수의 제1금속배선층에 적어도 하나의 제1 금속배선 상부에 배치된 제2 금속배선을 포함하는 것을 특징으로 하는 반도체장치의 금속배선층의 EM 테스트 패턴을 제공한다.An EM test pattern of a metal wiring layer of a semiconductor device is disclosed. The present invention relates to a test pattern of a semiconductor device, comprising: a plurality of first metal wires arranged on a semiconductor substrate having the same surface irregularities as an actual semiconductor device while maintaining a distance according to a minimum design rule from each other; And a second metal interconnection disposed on at least one first metal interconnection on the plurality of first metal interconnection layers. The EM test pattern of the metal interconnection layer of the semiconductor device is provided.

Description

반도체장치의 금속배선층의 EM 테스트 패턴EM test pattern of metallization layer in semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 의한 EM 테스트 패턴의 평면도이다.1 is a plan view of an EM test pattern according to the present invention.

Claims (1)

반도체장치의 테스트 패턴에 있어서, 실제의 반도체장치와 동일한 표면요철을 갖는 반도체기판 상에 서로 최소 디자인 룰에 의한 간격을 유지하면서 배치된 복수의 제1 금속배선; 및 상기 복수의 제1 금속배선층에 적어도 하나의 제1 금속배선 상부에 배치된 제2 금속배선을 포함하는 것을 특징으로 하는 반도체장치의 금속배선층의 EM 테스트 패턴.A test pattern of a semiconductor device, the test pattern comprising: a plurality of first metal wirings disposed on a semiconductor substrate having the same surface irregularities as an actual semiconductor device while maintaining a distance from each other by a minimum design rule; And a second metal wiring disposed on at least one first metal wiring on the plurality of first metal wiring layers. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950038992A 1995-10-31 1995-10-31 EM test pattern of metallization layer in semiconductor device KR970023951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950038992A KR970023951A (en) 1995-10-31 1995-10-31 EM test pattern of metallization layer in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950038992A KR970023951A (en) 1995-10-31 1995-10-31 EM test pattern of metallization layer in semiconductor device

Publications (1)

Publication Number Publication Date
KR970023951A true KR970023951A (en) 1997-05-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950038992A KR970023951A (en) 1995-10-31 1995-10-31 EM test pattern of metallization layer in semiconductor device

Country Status (1)

Country Link
KR (1) KR970023951A (en)

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