KR970019128A - A channel encoder and a channel decoder in a digital communication system - Google Patents

A channel encoder and a channel decoder in a digital communication system Download PDF

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Publication number
KR970019128A
KR970019128A KR1019950032564A KR19950032564A KR970019128A KR 970019128 A KR970019128 A KR 970019128A KR 1019950032564 A KR1019950032564 A KR 1019950032564A KR 19950032564 A KR19950032564 A KR 19950032564A KR 970019128 A KR970019128 A KR 970019128A
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South Korea
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bit streams
output
sequentially
multiplexer
channel
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KR1019950032564A
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Korean (ko)
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권오상
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배순훈
대우전자 주식회사
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Publication of KR970019128A publication Critical patent/KR970019128A/en

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Abstract

본 발명은 디지털 통신 시스템의 채널 엔코더 및 채널 디코더에 관한 것으로, 채널 엔코더는, 입력된 직열 비트 스트림을 1비트씩 순차적으로 분리하여 다수개의 병열 비트 스트림을 출력하는 멀티플레서(40)와, 상기 멀티플렉서(40)를 통해 출력된 다수개의 병열 비트 스트림을 각각 길쌈부호화하여 출력하는 다수개의 길쌈부호기(42-1~42-N) 및 상기 다수개의 길쌈부호기(42-1~42-N)를 통해 길쌈 부호화되어 출력된 다수개의 병열 비트스트림을 2비트씩 순차적으로 선택하여 직열 비트스트림을 출력하는 디멀티플렉서(44)를 포함하여 구성되는 한편, 채널 디코더는, 길쌈 부호화되어 입력된 직열 비트스트림 2비트씩 순차적으로 분리하여 다수개의 병열 비트 스트림을 출력하는 멀티플렉서(50)와 상기 멀티플렉서(50)를 통해 출력된 다수개의 병열 비트 스트림을 각각 길쌈 복호화하여 출력하는 다수개의 비터비 복호기(52-1~52-N) 및 상기 다수개의 비터비 복호기(52-1~52-N)를 통해 길삼 복호화되어 출력된 다수개의 병열 비트 스트림을 1비트씩 순차적으로 선택하여 직열 비트 스트림을 출력하는 디멀티플렉서(54)를 포함하여 구성됨에 따라 고속으로 채널 디코딩을 수행할 수 있어 고속의 디지털 서비스를 제공할 수 있는 것이다.The present invention relates to a channel encoder and a channel decoder of a digital communication system. The channel encoder includes: a multiplexer 40 for sequentially separating input serial bit streams by one bit and outputting a plurality of parallel bit streams, and the multiplexer. Weaving through a plurality of convolutional encoders 42-1 to 42-N and a plurality of convolutional encoders 42-1 to 42-N, which convolutionally encode and output a plurality of parallel bit streams output through 40, respectively. And a demultiplexer 44 which sequentially selects a plurality of coded parallel bitstreams sequentially by 2 bits and outputs a serial bitstream, while the channel decoder sequentially processes the bitstreams input by convolutional encoding. A multiplexer 50 for outputting a plurality of parallel bit streams and a plurality of parallel bit streams output through the multiplexer 50 are separated. A plurality of parallel bit streams decoded and output through a plurality of Viterbi decoders 52-1 to 52-N and each of the Viterbi decoders 52-1 to 52-N that are convolutionally decoded and outputted are 1 Since the demultiplexer 54 sequentially selects bit by bit and outputs a serial bit stream, channel decoding can be performed at high speed, thereby providing high-speed digital service.

Description

디지털 통신 시스템의 채널 엔코더 및 채널 디코더(A channel encoder and channel decoder in a digital communication system)A channel encoder and channel decoder in a digital communication system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명에 다른 디지털 통신 시스템의 채널 엔코더의 개략적인 구성도.5 is a schematic configuration diagram of a channel encoder of a digital communication system according to the present invention.

제6도는 본 발명에 따른 디지털 통신 시스템의 채널 디코더의 개략적인 구송도.6 is a schematic diagram of a channel decoder of a digital communication system according to the present invention.

Claims (2)

디지털 신호를 에러 정정 부호화하여 출력하는 디지털 통신 시스템의 채널 엔코더에 있어서, 채널 입력된 직열 비트 스트림을 1비트씩 순차적으로 분리하여 다수개의 병열 비트 스트림을 출력하는 멀티 플렉서(40)와, 상기 멀티플렉서(40)를 통해 출력된 다수개의 병열 비트 스트림을 각각 길쌈부호화하여 출력하는 다수개의 길쌈부호기(42-1~42-N) 및; 상기 다수개의 길쌈부호기(42-1~42-N)를 통해 길쌈 부호화 되어 출력된 다수개의병열 비트스트림을 2비트씩 순차적으로 선택하여 직열 비트 스트림을 출력하는 디멀티플렉서(44)를 포함하여 구성되는 것을 특징으로 하는 디지털 통신 시스템의 채널 엔코더.In the channel encoder of a digital communication system for error-correcting and outputting a digital signal, a multiplexer 40 for outputting a plurality of parallel bit streams by sequentially separating channel input serial bit streams by 1 bit, and the multiplexer A plurality of convolutional encoders 42-1 to 42-N that convolutionally encode and output a plurality of parallel bit streams output through 40; And a demultiplexer 44 which sequentially outputs a serial bit stream by sequentially selecting a plurality of parallel bit streams that are convolutionally encoded and output through the plurality of convolutional encoders 42-1 to 42-N. A channel encoder of a digital communication system. 에러 정정 부호화된 디지털 신호를 에러 정정 복호화하여 출력하는 디지털 통신 시스템의 채널 디코더에 있어서, 길쌈 부호화되어 입력된 직열 비트스티름 2비트씩 순차적으로 분리하여 다수개의 병열 비트스트림을 출력하는 멀티플렉서와, 상기 멀티플렉서(50)를 통해 출력된 다수개의 병열 비트 스트림을 각각 길쌈 복호화하여 출력하는 다수개의 비터비복호기(52-1~52-N) 및, 상기 다수개의 비터비복호기(52-1~52-N)를 통해 길쌈 복호화되어 출력된 다수개의 병열 비트 스트림을 1비트씩 순차적으로 선택하여 직열 비트 스트림을 출력하는 디멀티플렉서(54)를 포함하여 구성된 것을 특징으로 하는 디지털 통신 시스템의 채널 디코더.A channel decoder of an error correction coded digital signal outputted by error correction decoding, the channel decoder comprising: a multiplexer for outputting a plurality of parallel bitstreams sequentially separated by 2 bits of convolutional encoded input serial bitstreams; A plurality of Viterbi decoders 52-1 to 52-N and a plurality of Viterbi decoders 52-1 to 52-N that convolutionally decode and output a plurality of parallel bit streams output through the multiplexer 50, respectively. And a demultiplexer (54) for sequentially outputting a serial bit stream by sequentially selecting a plurality of parallel bit streams output by convolutional decoding through 1). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950032564A 1995-09-29 1995-09-29 A channel encoder and a channel decoder in a digital communication system KR970019128A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100540728B1 (en) * 1999-07-15 2006-01-12 후지쯔 가부시끼가이샤 Viterbi decoder and transmitting equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100540728B1 (en) * 1999-07-15 2006-01-12 후지쯔 가부시끼가이샤 Viterbi decoder and transmitting equipment

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