KR970018139A - Semiconductor Memory Device with Good Flatness - Google Patents

Semiconductor Memory Device with Good Flatness Download PDF

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Publication number
KR970018139A
KR970018139A KR1019950029301A KR19950029301A KR970018139A KR 970018139 A KR970018139 A KR 970018139A KR 1019950029301 A KR1019950029301 A KR 1019950029301A KR 19950029301 A KR19950029301 A KR 19950029301A KR 970018139 A KR970018139 A KR 970018139A
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KR
South Korea
Prior art keywords
semiconductor device
oxide film
good flatness
memory device
film
Prior art date
Application number
KR1019950029301A
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Korean (ko)
Inventor
이광재
김석규
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950029301A priority Critical patent/KR970018139A/en
Publication of KR970018139A publication Critical patent/KR970018139A/en

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

평탄성이 양호한 반도체 장치에 관한 것으로, 고온산화막과 층간평탄화막 사이에 차단막을 설치하여, 반도체 장치의 수율과 및 신뢰성이 향상될 수 있다.The present invention relates to a semiconductor device having good flatness, wherein a blocking film is provided between the high temperature oxide film and the interlayer planarization film, so that the yield and reliability of the semiconductor device can be improved.

Description

평탄성이 양호한 반도체 메모리 장치Semiconductor Memory Device with Good Flatness

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명에 따른 4M 에스램셀의 평탄화를 위한 반도체 장치 일부의 단면도이다.2A through 2C are cross-sectional views of a part of a semiconductor device for planarization of a 4M SRAM cell according to the present invention.

Claims (3)

평탄화가 필요하며, 반도체장치의 기판상에 형성된 층간절연막, 상기 층간절연막 상부에 형성된 고온산화막과 도전층을 가지는 반도체장치에 있어서, 상기 층간절연막과 상기 고온산화막 사이에 형성된 저온산화막을 가짐을 특징으로 하는 반도체장치.A semiconductor device having a planarization and an interlayer insulating film formed on a substrate of a semiconductor device and a high temperature oxide film and a conductive layer formed on the interlayer insulating film, wherein the low temperature oxide film is formed between the interlayer insulating film and the high temperature oxide film. A semiconductor device. 제1항에 있어서, 상기 저온산화막이 플라즈마산화막 또는 나이트라이드막임을 특징으로 하는 반도체 장치.The semiconductor device according to claim 1, wherein the low temperature oxide film is a plasma oxide film or a nitride film. 제1항에 있어서, 상기 층간절연막은 BPSG임을 특징으로 하는 반도체 장치.The semiconductor device according to claim 1, wherein the interlayer insulating film is BPSG. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950029301A 1995-09-07 1995-09-07 Semiconductor Memory Device with Good Flatness KR970018139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950029301A KR970018139A (en) 1995-09-07 1995-09-07 Semiconductor Memory Device with Good Flatness

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950029301A KR970018139A (en) 1995-09-07 1995-09-07 Semiconductor Memory Device with Good Flatness

Publications (1)

Publication Number Publication Date
KR970018139A true KR970018139A (en) 1997-04-30

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ID=66596252

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950029301A KR970018139A (en) 1995-09-07 1995-09-07 Semiconductor Memory Device with Good Flatness

Country Status (1)

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KR (1) KR970018139A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100452311B1 (en) * 1997-04-11 2005-01-17 삼성전자주식회사 Interlayer dielectric of semiconductor device and fabricating method thereof to stably use hto layer and bpsg layer without preventing silicide layer from being influenced by heat

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100452311B1 (en) * 1997-04-11 2005-01-17 삼성전자주식회사 Interlayer dielectric of semiconductor device and fabricating method thereof to stably use hto layer and bpsg layer without preventing silicide layer from being influenced by heat

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