KR970018022A - Manufacturing Method of Semiconductor Device Using Different Spacer Length - Google Patents

Manufacturing Method of Semiconductor Device Using Different Spacer Length Download PDF

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KR970018022A
KR970018022A KR1019950032201A KR19950032201A KR970018022A KR 970018022 A KR970018022 A KR 970018022A KR 1019950032201 A KR1019950032201 A KR 1019950032201A KR 19950032201 A KR19950032201 A KR 19950032201A KR 970018022 A KR970018022 A KR 970018022A
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spacer
forming
source
drain
oxide film
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KR1019950032201A
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Korean (ko)
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KR0147667B1 (en
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강덕동
서영우
홍원철
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

상이한 스페이서 길이를 이용한 반도체 소자의 제조방법에 관하여 기재하고 있다.A method for manufacturing a semiconductor device using different spacer lengths is described.

본 발명은 셀 어레이부, 주변 회로부의 NMOS 및 PMOS 영역에 각각 상이한 스페이서 길이를 이용한 반도체소자의 제조방법에 있어서, 각각의 영역에 대한 마스크 작업 후 식각에 의한 스페이서 형성 및 소오스/드레인 이온주입을 행하여 트랜지스터를 형성하는 제1실시예와 셀 어레이 영역의 스페이서와 폴리 패드를 먼저 형성하고 나중에 NMOS, PMOS 영역의 스페이서를 형성하여 트랜지스터를 완성하는 제2실시예에 관한 것이다. 따라서, 상이한 길이의 스페이서에 의해 각각의 트랜지스터가 적합한 전기적 특성을 가질 수 있을 뿐 아니라, 스페이서 형성과 소오스/드레인 이온주입이 일관되게 이루어지므로 별도의 마스크 작업이 불필요하여 공정을 간략화할 수 있다.The present invention provides a method of fabricating a semiconductor device using different spacer lengths in NMOS and PMOS regions of a cell array portion and a peripheral circuit portion, wherein after forming a mask for each region, spacer formation by etching and source / drain ion implantation are performed. A first embodiment of forming a transistor and a second embodiment of forming a spacer and a poly pad of a cell array region first, followed by a spacer of an NMOS and PMOS region to complete a transistor. Therefore, not only can each transistor have suitable electrical characteristics by spacers of different lengths, but also spacer formation and source / drain ion implantation are consistently performed, thus eliminating the need for a separate mask and simplifying the process.

Description

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제8C도는 본 발명의 제1실시예에 의한 반도체 소자 형성 공정도이다.2A to 8C are process charts for forming a semiconductor device according to the first embodiment of the present invention.

Claims (11)

상이한 스페이서 길이를 이용한 반도체 소자의 제조 방법에 있어서, 반도체 기판 상에 게이트 산화막, 게이트 전극용의 저 저항도전층, 적정 두께의 산화막을 차례로 증착하는 제1단계; 상기 게이트 산화막, 저 저항 도전층 및 패터닝하여 게이트 전극을 형성하는 제2단계; 게이트 전극이 형성된 상기 결과물 상에 LDD구조 형성을 위한 N-이온주입이 행해진 상기 결과물 상에 스페이서 형성을 위한 제1산화막을 증착한 후 N+ 소오스/드레인 마스크를 이용한 사진, 식각공정을 통하여 NMOS 스페이서를 형성하는 제4단계; NMOS 스페이서가 형성된 상기 결과물 상에 N+ 소오스/드레인 이온주입을 하여 NMOS 트랜지스터를 형성하는 제5단계; PMOS 트랜지스터의 소오스/드레인에서 게이트 전극과 소오스/드레인과의 완전한 오버랩을 위해 상기 제1산화막을 소정 두께가 되도록 습식식각을 행하는 제6단계; 습식식각된 상기 제1산화막을 P+ 소오스/드레인 마스크를 이용한 사진, 식각공정을 통하여 PMOS 스페이서를 형성하는 제7단계; PMOS 스페이서가 형성된 상기 결과물상에 P+ 소오스/드레인 이온주입을 하여 PMOS 트랜지스터를 형성하는 제8단계; 및 상기 결과물 상에 제2산화막을 증착한 후 셀 오픈 마스크를 이용한 사진, 식각공정을 통하여 셀 어레이 스페이서를 형성하는 제9단계를 구비하여 이루어지는 것을 특징으로 하는 상이한 스페이서 길이를 이용한 반도체 소자 제조방법.A method of manufacturing a semiconductor device using different spacer lengths, comprising: a first step of sequentially depositing a gate oxide film, a low resistance conductive layer for a gate electrode, and an oxide film having an appropriate thickness on a semiconductor substrate; A second step of forming a gate electrode by patterning the gate oxide layer, the low resistance conductive layer, and the second electrode; After depositing a first oxide film for forming a spacer on the resultant N-ion implantation for forming an LDD structure on the resultant gate electrode formed thereon, the NMOS spacer was formed through a photo-etching process using an N + source / drain mask. Forming a fourth step; A fifth step of forming an NMOS transistor by performing N + source / drain ion implantation on the resultant NMOS spacer formed thereon; A sixth step of wet etching the first oxide layer to a predetermined thickness for complete overlap between the gate electrode and the source / drain in a source / drain of a PMOS transistor; Forming a PMOS spacer by wet etching the first oxide layer using a P + source / drain mask and etching the first oxide layer; An eighth step of forming a PMOS transistor by performing P + source / drain ion implantation on the resultant PMOS spacer; And a ninth step of forming a cell array spacer through an etching process and a photo using a cell open mask after depositing a second oxide film on the resultant. 제1항에 있어서, 상기 제1단계의 저 저항 도전층은 폴리 실리콘막과 소정 두께의 실리사이드막으로 형성하는 것을 특징으로 하는 상이한 스페이서 길이를 이용한 반도체 소자 제조방법.2. The method of claim 1, wherein the low resistance conductive layer of the first step is formed of a polysilicon film and a silicide film having a predetermined thickness. 제2항에 있어서, 소정 두께의 실리사이드막은 텅스텐 실리사이드막으로 형성하는 것을 특징으로 하는 상이한 스페이서 길이를 이용한 반도체 소자 제조방법.3. The method of claim 2, wherein the silicide film having a predetermined thickness is formed of a tungsten silicide film. 제1항에 있어서, 상기 제4단계에서의 제1산화막은 1500∼2000Å으로 형성하는 것을 특징으로 하는 상이한 스페이서 길이를 이용한 반도체 소자 제조방법.2. The method of claim 1, wherein the first oxide film in the fourth step is formed at 1500 to 2000 microns. 제1항에 있어서, 상기 제5단계의 N+ 소오스/드레인 이온주입은 상기 제4단계중 상기 제1산화막을 HF 포함 용액에서 200∼250Å정도 식각한 후 상기 NMOS 스페이서를 형성하고, 감광막을 제거한 후에 진행하는 것을 특징으로 하는 상이한 스페이서 길이를 이용한 반도체 소자 제조방법.The method of claim 1, wherein the N + source / drain ion implantation of the fifth step is performed by etching the first oxide film in an HF-containing solution at about 200 to 250 microns in the fourth step to form the NMOS spacer, and then removing the photoresist film. A method of manufacturing a semiconductor device using different spacer lengths, characterized in that it proceeds. 제1항에 있어서, 상기 제9단계의 제2산화막은 1000∼1500Å으로 형성하는 것을 특징으로 하는 상이한 스페이서 길이를 이용한 반도체 소자 제조방법.The method of claim 1, wherein the second oxide film of the ninth step is formed to have a thickness of 1000 to 1500 Å. 상이한 스페이서 길이를 이용한 반도체 소자의 제조방법에 있어서, 반도체 기판상에 게이트 산화막, 게이트 전극용의 저 저항도전층, 적정 두께의 산화막을 차례로 증착하는 제1단계; 상기 제1단계 후에 소정의 크기로 게이트 전극을 패터닝한 후 LDD 구조 형성을 위한 N- 이온주입을 NMOS, PMOS, 셀 어레이 전면에 실시하는 제2단계; 상기 제2단계 후에 스페이서 형성을 위한 제3산화막을 증착하는 제3단계; 상기 제3단계후에 셀 오픈 마스크를 이용, 식각하여 셀 어레이영역의 스페이서를 형성하는 제4단계; 상기 제4단계 후에 폴리실리콘을 증착하고, 식각하여 축전기 콘택 부위와 비트라인 콘택 부위에 폴리 패드를 형성하는 제5단계; 상기 제5단계 후에 N+ 소오스/드레인 마스크를 이용한 사진, 식각공정을 통하여 NMOS 스페이서를 형성한 후 N+ 소오스/드레인 이온주입을 하여 NMOS 트랜지스터를 형성하는 제6단계; 상기 제6단계 후에 PMOS 트랜지스터의 소오스/드레인에서 게이트 전극과 소오스/드레인과의 완전한 오버랩을 위해 상기 제3산화막을 소정 두께가 되도록 습식식각을 행하는 제7단계; 상기 제7단계 후에 습식식각된 상기 제3산화막을 P+ 소오스/드레인 마스크를 이용, 식각하여 PMOS 스페이서를 형성하는 제8단계; 및 상기 제8단계 후에 P+ 소오스/드레인 이온주입을 하여 PMOS 트랜지스터를 형성하는 제9단계를 구비하여 이루어지는 것을 특징으로 하는 상이한 스페이서 길이를 이용한 반도체 소자 제조방법.A method of manufacturing a semiconductor device using different spacer lengths, comprising: a first step of sequentially depositing a gate oxide film, a low resistance conductive layer for a gate electrode, and an oxide film having an appropriate thickness on a semiconductor substrate; A second step of patterning a gate electrode to a predetermined size after the first step, and then performing N-ion implantation on the entire surface of the NMOS, PMOS, or cell array to form an LDD structure; A third step of depositing a third oxide film for forming a spacer after the second step; A fourth step of forming a spacer of the cell array region by etching by using a cell open mask after the third step; Depositing and etching polysilicon after the fourth step to form a poly pad in the capacitor contact portion and the bit line contact region; A sixth step of forming an NMOS transistor by forming an NMOS spacer through a photolithography and an etching process using an N + source / drain mask after the fifth step and performing N + source / drain ion implantation; Performing a seventh step of wet etching the third oxide layer to a predetermined thickness in order to completely overlap the gate electrode and the source / drain in the source / drain of the PMOS transistor after the sixth step; An eighth step of etching the third oxide film wet-etched after the seventh step using a P + source / drain mask to form a PMOS spacer; And a ninth step of forming a PMOS transistor by performing P + source / drain ion implantation after the eighth step. 제7항에 있어서, 상기 제1단계의 저 저항 도전층은 폴리 실리콘막과 소정 두께의 실리사이드막인 것을 특징으로 하는 상이한 스페이서 길이를 이용한 반도체 소자 제조방법.The method of claim 7, wherein the low resistance conductive layer of the first step is a polysilicon film and a silicide film having a predetermined thickness. 제8항에 있어서, 소정 두께의 실리사이드막은 텅스텐 실리사이드막으로 형성하는 것을 특징으로 하는 상이한 스페이서 길이를 이용한 반도체 소자 제조방법.The method of claim 8, wherein the silicide film having a predetermined thickness is formed of a tungsten silicide film. 제7항에 있어서, 상기 제3단계의 제3산화막은 2000∼2500Å으로 형성하는 것을 특징으로 하는 상이한 스페이서 길이를 이용한 반도체 소자 제조방법.8. The method of claim 7, wherein the third oxide film of the third step is formed at 2000 to 2500 microns. 제7항에 있어서, 상기 제6단계의 N+ 소오스/드레인 이온주입은 상기 제3산화막을 HF 포함 용액에서 200∼250Å정도 식각한 후 상기 NMOS 스페이서를 형성하고, 감광막을 제거한 후에 진행하는 것을 특징으로 하는 상이한 스페이서 길이를 이용한 반도체 소자 제조방법.8. The method of claim 7, wherein the N + source / drain ion implantation of the sixth step is performed by etching the third oxide film in an HF-containing solution at about 200 to 250 microns, thereby forming the NMOS spacer and removing the photoresist film. A semiconductor device manufacturing method using different spacer lengths. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950032201A 1995-09-27 1995-09-27 Fabrication method for semiconductor device using different space length KR0147667B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487504B1 (en) * 1997-12-12 2005-07-07 삼성전자주식회사 A method of forming different gate spacers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487504B1 (en) * 1997-12-12 2005-07-07 삼성전자주식회사 A method of forming different gate spacers

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