KR970017759A - Fuse stage selection circuit of semiconductor device - Google Patents
Fuse stage selection circuit of semiconductor device Download PDFInfo
- Publication number
- KR970017759A KR970017759A KR1019950030034A KR19950030034A KR970017759A KR 970017759 A KR970017759 A KR 970017759A KR 1019950030034 A KR1019950030034 A KR 1019950030034A KR 19950030034 A KR19950030034 A KR 19950030034A KR 970017759 A KR970017759 A KR 970017759A
- Authority
- KR
- South Korea
- Prior art keywords
- selection circuit
- fuse
- node
- mode selection
- semiconductor device
- Prior art date
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- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체 장치의 퓨즈용단 선택회로에 관한 것으로서, 특히 모드선택회로부와 확인회로부를 구비한 반도체 장치의 퓨즈용단 선택회로에 있어서, 확인회로부는 대응하는 외부신호가 인가되는 패드와 노드C 사이에 연결된 다이오드; 모드선택회로부의 모드선택신호가 게이트에 인가되고 드레인이 노드C에 연결되고 소오스가 접지된 트랜지스터를 구비한 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse short selection circuit of a semiconductor device, and more particularly to a fuse short selection circuit of a semiconductor device having a mode selection circuit section and a verification circuit section, wherein the verification circuit section is provided between a pad and a node C to which a corresponding external signal is applied. Connected diodes; And a transistor in which the mode selection signal of the mode selection circuit unit is applied to the gate, the drain is connected to the node C, and the source is grounded.
따라서, 본 발명에서는 웨이퍼 및 패키지 레벨에서 퓨즈용단이 가능하고 회로구성의 간략화로 면적을 줄일 수 있다Therefore, in the present invention, fuse blown at the wafer and package level is possible, and the area can be reduced by simplifying the circuit configuration.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 의한 퓨즈용단 선택회로의 구성을 나타낸 회로도.2 is a circuit diagram showing the configuration of a fuse selection circuit for fuses according to the present invention;
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950030034A KR970017759A (en) | 1995-09-14 | 1995-09-14 | Fuse stage selection circuit of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950030034A KR970017759A (en) | 1995-09-14 | 1995-09-14 | Fuse stage selection circuit of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970017759A true KR970017759A (en) | 1997-04-30 |
Family
ID=66615292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950030034A KR970017759A (en) | 1995-09-14 | 1995-09-14 | Fuse stage selection circuit of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970017759A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100458884B1 (en) * | 2000-12-27 | 2004-12-03 | 가부시끼가이샤 도시바 | Fuse circuit |
KR100471139B1 (en) * | 1997-11-18 | 2005-06-07 | 삼성전자주식회사 | Semiconductor memory device having mode setting circuit |
KR100761399B1 (en) * | 2000-12-30 | 2007-09-27 | 주식회사 하이닉스반도체 | Redundancy circuit |
-
1995
- 1995-09-14 KR KR1019950030034A patent/KR970017759A/en not_active Application Discontinuation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100471139B1 (en) * | 1997-11-18 | 2005-06-07 | 삼성전자주식회사 | Semiconductor memory device having mode setting circuit |
KR100458884B1 (en) * | 2000-12-27 | 2004-12-03 | 가부시끼가이샤 도시바 | Fuse circuit |
KR100761399B1 (en) * | 2000-12-30 | 2007-09-27 | 주식회사 하이닉스반도체 | Redundancy circuit |
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WITN | Withdrawal due to no request for examination |