KR970017677A - Nonvolatile Semiconductor Memory Device With Reduced Area - Google Patents

Nonvolatile Semiconductor Memory Device With Reduced Area Download PDF

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Publication number
KR970017677A
KR970017677A KR1019950033094A KR19950033094A KR970017677A KR 970017677 A KR970017677 A KR 970017677A KR 1019950033094 A KR1019950033094 A KR 1019950033094A KR 19950033094 A KR19950033094 A KR 19950033094A KR 970017677 A KR970017677 A KR 970017677A
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KR
South Korea
Prior art keywords
memory device
nonvolatile semiconductor
semiconductor memory
bit line
common source
Prior art date
Application number
KR1019950033094A
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Korean (ko)
Other versions
KR100197553B1 (en
Inventor
한욱기
용명식
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950033094A priority Critical patent/KR100197553B1/en
Publication of KR970017677A publication Critical patent/KR970017677A/en
Application granted granted Critical
Publication of KR100197553B1 publication Critical patent/KR100197553B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

1 청구 범위에 기재된 발명이 속하는 기술분야1 The technical field to which the invention described in the claims belong

불휘발성 반도체 메모리 장치에 관한 것이다.A nonvolatile semiconductor memory device.

2. 발명이 해결하려고 하는 기술직 과제2. The technical task the invention seeks to solve

감소된 면적을 가지는 불휘발성 반도체 메모리 장치를 제공함에 있다.Disclosed is a nonvolatile semiconductor memory device having a reduced area.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

폴디드 비트라인의 좌우측에 접속된 복수개의 메모리 트랜지스터들을 선택하기 위한 선택 트랜지스터를 각 비트라인의 일측과 타측에 각기 하나씩 접속하고, 상기 홀수번째 비트라인에는 제1공통소오스라인을 접속하고, 상기 짝수번깨 비트라인에는 제2공통소오스라인을 접속한다.A select transistor for selecting a plurality of memory transistors connected to the left and right sides of the folded bit line is connected to one side and the other side of each bit line, and a first common source line is connected to the odd bit line, and the even number is A second common source line is connected to the flash bit line.

4. 발명의 중요한 용도4. Important uses of the invention

불휘발성 반도체 메모리 장치에 적합하게 사용된다.It is suitably used for a nonvolatile semiconductor memory device.

Description

감소된 면적을 가지는 불휘발성 반도체 메모리 장치Nonvolatile Semiconductor Memory Device With Reduced Area

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따라 폴디드 비트라인을 선택하기 위한 회로도.3 is a circuit diagram for selecting a folded bit line in accordance with the present invention.

Claims (2)

폴디드 비트라인의 좌우측에 접속된 복수개의 메모리 트랜지스터들을 선택하기 위한 선택 트랜지스터들과, 공통소오스라인를 적어도 구비하는 불휘발성 반도체 메모리 장치에 있어서; 상기 폴디드 비트라인의 좌우측에 접속된 복수개의 메모리 트랜지스터들을 선택하기 위한 선택 트랜지스터를 각 비트라인의 일측과 타측에 각기 하나씩 접속하고, 상기 홀수번째 비트라인에는 제1공통소오스라인을 접속하고, 상기 짝수번째 비트라인에는 제2공통소오스라인을 접속하는 불휘발성 반도체 메모리 장치.A nonvolatile semiconductor memory device comprising: select transistors for selecting a plurality of memory transistors connected to left and right sides of a folded bit line, and at least a common source line; A selection transistor for selecting a plurality of memory transistors connected to the left and right sides of the folded bit line is connected to one side and the other side of each bit line, and a first common source line is connected to the odd bit line; A nonvolatile semiconductor memory device for connecting a second common source line to an even bit line. 제1항에 있어서, 상기 제1 및 제2공통소오스라인에 인가되는 신호는 서로 상반된 전압이 인가됨을 특징으로 하는 불휘발성 반도체 메모리 장치.The nonvolatile semiconductor memory device of claim 1, wherein voltages applied to the first and second common source lines are opposite to each other. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950033094A 1995-09-29 1995-09-29 Non-volatile semiconductor memory device with reduced area KR100197553B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950033094A KR100197553B1 (en) 1995-09-29 1995-09-29 Non-volatile semiconductor memory device with reduced area

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950033094A KR100197553B1 (en) 1995-09-29 1995-09-29 Non-volatile semiconductor memory device with reduced area

Publications (2)

Publication Number Publication Date
KR970017677A true KR970017677A (en) 1997-04-30
KR100197553B1 KR100197553B1 (en) 1999-06-15

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Family Applications (1)

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KR1019950033094A KR100197553B1 (en) 1995-09-29 1995-09-29 Non-volatile semiconductor memory device with reduced area

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Country Link
KR (1) KR100197553B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100672121B1 (en) * 2005-01-12 2007-01-19 주식회사 하이닉스반도체 Non-volatile memory device and programming/reading method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100672121B1 (en) * 2005-01-12 2007-01-19 주식회사 하이닉스반도체 Non-volatile memory device and programming/reading method thereof

Also Published As

Publication number Publication date
KR100197553B1 (en) 1999-06-15

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