KR970014373A - Video encoder and decoder - Google Patents

Video encoder and decoder Download PDF

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Publication number
KR970014373A
KR970014373A KR1019950028320A KR19950028320A KR970014373A KR 970014373 A KR970014373 A KR 970014373A KR 1019950028320 A KR1019950028320 A KR 1019950028320A KR 19950028320 A KR19950028320 A KR 19950028320A KR 970014373 A KR970014373 A KR 970014373A
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South Korea
Prior art keywords
image
discrete cosine
inverse
quantizer
scalar
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KR1019950028320A
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Korean (ko)
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KR100204468B1 (en
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윤성욱
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배순훈
대우전자 주식회사
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Publication of KR970014373A publication Critical patent/KR970014373A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/94—Vector quantisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Discrete Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Image Processing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

본 발명은 영상 부호기 및 영상 복호기에 관한 것으로, 이산여현 변환된 데이타를 복수개의 벡터 양자화기를 이용하여 벡터 양자화함과 동시에 스칼라 양자화한 후 왜곡치가 가장 적은 양자화방식으로 부호화된 영상 시퀀스를 송신하고, 수신측에서는 상기 영상 시퀀스를 수신한 후 복수개의 벡터 양자화 복호기와 스칼라 양자화 복호기에서 복호하고 송신시 선택된 해당 부호기에 해당하는 복호기의 출력을 선택하여 역이산 여현 변환하여 출력하도록 되어있다.The present invention relates to an image encoder and an image decoder, wherein the discrete cosine transformed data is subjected to vector quantization using a plurality of vector quantizers, and simultaneously scalar quantized to transmit an image sequence encoded by a quantization method having the least distortion. After receiving the video sequence, the decoder decodes a plurality of vector quantization decoders and scalar quantization decoders, and selects an output of a decoder corresponding to the corresponding encoder selected at the time of transmission to perform inverse discrete cosine conversion.

Description

영상 부호기 및 복호기Video encoder and decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 영상 부호기를 도시한 블럭도.2 is a block diagram showing a video encoder according to the present invention.

제3도는 본 발명에 따른 영상 복호기를 도시한 블럭도이다.3 is a block diagram showing an image decoder according to the present invention.

Claims (4)

프레임 메모리(21)로부터 영상데이타를 입력받아 이산여현 변환하는 이산여현 변환기(22), 상기 이산여현 변환기(22)의 출력을 벡터양자화하는 적어도 하나 이상의 벡터 양자화기(23~25), 상기 이산여현 변환기(22)의 출력을 스칼라 양자화하는 스칼라 양자화기(26), 상기 벡터 양자화기로부터 왜곡치입력 받아 비교한 후 최적의 양자화 방식을 선택하기 위한 선택제어신호를 발생하는 판단부(28) 및 상기 벡터 양자화기 및 스칼라 양자화기의 출력을 입력받아 상기 판단부(28)의 출력에 따라 선택하여 압축부호화된 영상을 출력하는 선택기로 구성되는 것을 특징으로 하는 영상 부호기.A discrete cosine transformer 22 for receiving the image data from the frame memory 21 and performing a discrete cosine conversion, at least one vector quantizer 23 to 25 for quantizing the output of the discrete cosine converter 22, and the discrete cosine. A scalar quantizer 26 for scalar quantizing the output of the transformer 22, a judging unit 28 for receiving a distortion value input from the vector quantizer, comparing the distortion value, and generating a selection control signal for selecting an optimal quantization scheme; And a selector configured to receive the outputs of the vector quantizer and the scalar quantizer, and output the compressed coded image according to the output of the determination unit (28). 제1항에 있어서, 상기 선택기는 멀티플렉서(27)로 구현되는 것을 특징으로 하는 영상 부호기.The video encoder according to claim 1, wherein the selector is implemented with a multiplexer (27). 이산여현 변환된 영상 데이타를 적어도 하나 이상의 벡터 양자화기 및 스칼라 양자화기에 의해 부호화된 영상 시퀀스를 수신한 후 복호하는 영상 복호기에 있어서, 상기 수신된 영상 시퀀스에서 영상신호와 선택제어신호를 분리하는 분류기(31), 상기 분류기(31)로부터 영상 시퀀스를 입력받아 역벡터 양자화하는 적어도 하나 이상의 역벡터 양자화기(32~34), 상기 분류기(31)로부터 영상 시퀀스를 입력받아 역스칼라 양자화하는 역스칼라 양자화기 (35) 및 상기 분류기(31)로부터 선택제어신호(SEL)를 입력받아 상기 역벡터 양자화기 및 역스칼라 양자화기의 출력중 하나를 선택하는 선택기 및 상기 선택기의 출력을 입력받아 역 이산여현 변환하는 역이산 여현 변환기(37)가 구비되는 영상 복호기.An image decoder for decoding a discrete cosine transformed image data after receiving an image sequence encoded by at least one vector quantizer and a scalar quantizer, comprising: a classifier for separating an image signal and a selection control signal from the received image sequence ( 31) at least one inverse vector quantizer 32 to 34 for receiving an inverse vector quantized image from the classifier 31 and an inverse scalar quantizer for receiving inverse scalar quantized image from the classifier 31. (35) and a selector for receiving a selection control signal SEL from the classifier 31 and selecting one of the outputs of the inverse vector quantizer and the inverse scalar quantizer, and an output of the selector for inverse discrete cosine conversion. An image decoder provided with an inverse discrete cosine converter 37. 제3항에 있어서, 상기 선택기는 멀티플렉서(36)로 구현되는 것을 특징으로 하는 영상 복호기.4. The video decoder of claim 3, wherein the selector is implemented with a multiplexer (36). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950028320A 1995-08-31 1995-08-31 An image encoder and decoder KR100204468B1 (en)

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KR100204468B1 KR100204468B1 (en) 1999-06-15

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KR101902933B1 (en) * 2009-12-16 2018-10-01 한국전자통신연구원 Apparatus for image coding/decoding and the method thereof

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