KR970014350A - Video signal coding device - Google Patents

Video signal coding device Download PDF

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Publication number
KR970014350A
KR970014350A KR1019950027283A KR19950027283A KR970014350A KR 970014350 A KR970014350 A KR 970014350A KR 1019950027283 A KR1019950027283 A KR 1019950027283A KR 19950027283 A KR19950027283 A KR 19950027283A KR 970014350 A KR970014350 A KR 970014350A
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KR
South Korea
Prior art keywords
length
barrel shifter
code
variable length
data
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KR1019950027283A
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Korean (ko)
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KR100195095B1 (en
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김재현
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/93—Run-length coding

Abstract

본 발명은 영상신호 부호화장치에 관한 것으로서, 부호화하고자 입력되는 소스화상신호를 이산여현변환하는 이산여현변환기, 이산여현변환기된 소스화상신호를 소정의 양자화 스텝사이즈로 양자화하는 양자화기, 양자화된 소스화상신호를 런 렝스 부호화기, 가변장 코드워드와 코드길이를 저장하는 메모리와 런렝쓰 부호화된 심볼에 해당하는 가변장 코드워드를 상기 메모리로부터 독출하고, 해당하는 코드길이를 이용하여 고정된 길이로 연결하여 출력하는 가변장 부호화기로 구성된다. 따라서 영상신호를 일정 단위로 구획하여 압축 부호화를 수행할 경우에 발생되는 가변장 부호비트를 연결하여 고정된 코드길이를 출력하는 것을 실시간으로 구현함으로써 DVCR 등에 용이하게 적용할 수 있다.The present invention relates to a video signal encoding apparatus, comprising: a discrete cosine transformer for discrete cosine transforming a source image signal input for encoding, a quantizer for quantizing a discrete cosine transformed source image signal to a predetermined quantization step size, and a quantized source image The signal is read from the memory with a run length encoder, a variable length codeword and a code length, and a variable length codeword corresponding to a run length coded symbol, and connected to a fixed length using the corresponding code length. It consists of a variable length encoder to output. Therefore, by outputting a fixed code length by connecting variable-length code bits generated when performing compression encoding by dividing the video signal into a predetermined unit, it can be easily applied to DVCR.

Description

영상신호 부호화장치Video signal coding device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 영상신호 부호화장치의 일실시예에 따른 블럭도이다.1 is a block diagram according to an embodiment of a video signal encoding apparatus according to the present invention.

Claims (4)

부호화하고자 입력되는 소스화상신호를 이산여현변환하는 이산여현변환기; 상기 이산여형변환기된 소스화상신호를 소정의 양자화 스텝사이즈로 양자화하는 양자화기; 상기 소스화상신호를 런렝쓰 부호화하는 런렝쓰 부호화기; 가변장 코드워드와 코드길이를 저장하는 메모리; 상기 런렝쓰 부호화된 심볼에 해당하는 가변장 코드워드를 상기 메모리로부터 독출하고, 해당하는 코드길이를 이용하여 고정된 길이로 연결하여 출력하는 가변장 부호화기; 및 상기 가변장 부호화기에서 가변장 부호화된 데이터를 소정 형태로 재정렬하여 출력하는 정렬기를 포함하는 것을 특징으로 하는 영상신호 부호화장치.A discrete cosine transformer for discrete cosine transforming the input image signal to be encoded; A quantizer for quantizing the discrete convolutional source image signal to a predetermined quantization step size; A run length encoder to run length encode the source image signal; A memory for storing variable length codewords and code lengths; A variable length encoder that reads a variable length codeword corresponding to the run-length coded symbol from the memory and connects the variable length codeword to a fixed length using a corresponding code length; And an aligner for rearranging the variable length coded data by the variable length encoder into a predetermined form and outputting the rearranged data. 제1항에 있어서, 상기 가변장 부호화기는 가변장 부호화된 코드워드를 매 클럭마다 해당 코드길이 만큼식 쉬프트시키는 제1배럴 쉬프터; 상기 제1배럴 쉬프터에서 쉬프트되는 비트수를 누적하여 해당 데이터가 전송되어야 할 시점을 제어하는 제어부; 상기 제어부의 제어하에, 상기 제1배럴 쉬프터에서 출력되는 데이터를 일정 단위로 출력하는 제2배럴 쉬프터; 및 상기 제어부의 제어하에, 상기 제2배럴 쉬프터에서 출력되는 데이터 중 블록단위로 일정 크기내에서 해당하는 데이터와 이를 초과하는 데이터를 구별하여 출력하는 멀티플렉서를 구비하는 것을 특징으로 하는 영상신호 부호화장치.The variable length encoder of claim 1, further comprising: a first barrel shifter configured to shift the variable length coded codeword by a corresponding code length every clock; A controller which accumulates the number of bits shifted in the first barrel shifter and controls a time point at which the corresponding data should be transmitted; A second barrel shifter configured to output data output from the first barrel shifter in a predetermined unit under the control of the controller; And a multiplexer for distinguishing and outputting the corresponding data and the data exceeding the data within a predetermined size in block units among the data output from the second barrel shifter under the control of the controller. 제2항에 있어서, 상기 제1배럴 쉬프터의 입력은 최대 16비트 단위의 코드워드에 해당하는 코드길이이며, 상기 코드길이는 상기 제어부에서 누적되어 상기 제2배럴 쉬프터에서 출력되는 코드워드의 코드길이를 제어하는 것을 특징으로 하는 영상신호 부호화장치.3. The code length of claim 2, wherein an input of the first barrel shifter is a code length corresponding to a codeword of a maximum of 16 bits, and the code length is accumulated in the control unit and outputted from the second barrel shifter. Image signal encoding apparatus characterized in that for controlling. 제2에 있어서, 상기 런랭쓰 부호화기에서 출력되는 심볼의 코드길이가 29비트인 경우, 16비트와 13비트로 분리되고, 각각 독립적인 코드워드와 코드길이로 출력함으로써 16비트 단위의 상기 제1 및 제2배럴 쉬프터가 매 클럭마다 동작이 가능하도록 하는 것을 특징으로 하는 영상신호 부호화장치.The method of claim 2, wherein when the code length of the symbol output from the run length encoder is 29 bits, the first length and the first length and the 16th bit unit are separated by 16 bits and 13 bits, respectively, and outputted as independent codewords and code lengths. And a two barrel shifter capable of operating every clock. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950027283A 1995-08-29 1995-08-29 Image signal encoding apparatus KR100195095B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100846870B1 (en) * 2006-07-06 2008-07-16 한국전자통신연구원 Apparatus and method of multi-stage, multi-dimensional transform based on multiple unit blocks

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100846870B1 (en) * 2006-07-06 2008-07-16 한국전자통신연구원 Apparatus and method of multi-stage, multi-dimensional transform based on multiple unit blocks
US8582657B2 (en) 2006-07-06 2013-11-12 Electronics And Telecommunications Research Institute Multi-dimensional and multi-stage transforming apparatus and method

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