KR970014338A

KR970014338A - STB's shared memory structure

Info

Publication number: KR970014338A
Application number: KR1019950023691A
Authority: KR
Inventors: 이대형
Original assignee: 구자홍; 엘지전자 주식회사
Priority date: 1995-08-01
Filing date: 1995-08-01
Publication date: 1997-03-29

Abstract

본 발명은 에스티비(STB:Set Top Box)에 관한 것으로서, 종래에는 STB용 상(Image)의 크기가 720*480이기 때문에 프레임 버퍼의 크기도 1MByte 정도가 필요하게 되면서, 상기 STB를 통해 TV에 공급되는 화면은 항상 하나이므로 화상용 프레임 버퍼로 이루어진 MPEG메로리부와 그래픽 메모리부는 같은 크기와 위치를 갖게 된다.The present invention relates to a STB (Set Top Box), and since the size of the image for the STB is 720 * 480, the size of the frame buffer is also required about 1 MByte, so that the TV is connected to the TV through the STB. Since there is always one screen to be supplied, the MPEG memory part and the graphic memory part, which are frame buffers for pictures, have the same size and position.

즉, 상기 MPEG메모리부의 이동화상(Moving Pictuve)과 그래픽 메모리부의 그래픽 상(Graphic Image)이 같은 화면상에 표시되면서, 서로 분리된 메모리상에 저장된 데이타를 다시 오버레이 제어부에 의해 합성시키므로서, 메모리의 사용량 증가 및 전체적인 시스템이 복잡해지면서 가격이 상승하는 문제점이 있었다.That is, while the moving picture of the MPEG memory part and the graphic image of the graphic memory part are displayed on the same screen, the data stored on the memory separated from each other is synthesized by the overlay control part again, thereby There was a problem that the price increases as usage increases and the overall system becomes complicated.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 속도가 빠르고 가격이 비슷한 동기식 디램(Synchronous DRAM)을 MPEG메모리로 사용하면서, 상기 MPEG메모리를 메모리 제어부를 통해 제어하므로서, 프레임 버퍼의 영역을 그래픽 제어부가 그래픽 메모리로 공용할 수 있도록 하여 그래픽 오버레이를 특별한 하드웨어없이 사용가능하게 하고, 이에 따라 메모리의 용량감소 및 전체적인 시스템이 간단해 지면서 원가절감을 이룰수있는 에스티비(STB)의 공용 메모리 구조이다.Therefore, in order to solve the above problems, the present invention uses a synchronous DRAM, which is similar in speed and price, as the MPEG memory, and controls the MPEG memory through the memory controller, thereby controlling the area of the frame buffer. It is a STB shared memory structure that enables the graphic overlay to be used as a graphic memory so that the graphic overlay can be used without special hardware, thereby reducing the memory capacity and simplifying the overall system.

Description

STB's shared memory structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

Claims

An interface unit 11 for simultaneously receiving a graphic data including menu selection and schedule information and moving picture MPEG data corresponding to the selected menu through a network; and the interface A transport demultiplexer 12 which separates and transmits graphic data and MPEG data simultaneously received by the unit 11, and decodes the separated transmitted MPEG data to MPEG RGB data / ads. MPEG video decoder 13 for reproducing and outputting, a graphic controller 14 for reproducing and outputting the separated and transmitted graphic data as graphic RGB data / address, the MPEG video decoder 13 and graphic controlling unit ( 14) Synchronous DRAM 16 is controlled by adjusting the DRAM access of the MPEG RGB data / address and the graphic RGB data / address reproduced and output in (DRAM Access). The memory controller 15 for controlling the image and the combined digital RGB by overlaying the MPGE RGB data / address and graphic RGB data / address whose DRAM access is adjusted according to the control of the memory controller 15 are used as image frame buffers. When storing in the (Frame Buffer) area, the digital synchronous DRAM unit 16 and the digital RGB of the display part stored in the frame buffer area of the synchronous DRAM unit 16 are stored in the NTSC (National Telegraph System Committee). A shared memory structure of STB composed of NTSC encoder 17 for outputting analog video.

The memory control unit (15) according to claim 1, wherein the memory control unit (15) has an MPEG buffer stage (18) for latching MPEG RGB data / address reproduced and output from the MPEG image decoder (13), and the reproduction output from the graphic control unit (14). MPEG RGB addresses that are reproduced and output by the MPEG, the video decoder 13 and the graphic controller 14 according to the graphic buffer stage 19 for latching the graphic RGB data / address and the input video enable signal. An address path control stage 20 for supplying the graphic RGB addresses to the address table 21, an address table 21 for storing the graphic RGB addresses under the control of the address path control stage 20, AND logic 22 for adjusting the data / address path control stage 23 according to the address table 21 and the enable signal, and MPEG RGB data / address under the control of the AND logic 22. And graphics MPEG RGB Other / to the address control of the shared memory structure S. Executive (STB), characterized in that consisting of data / address path control stage (23) for outputting a synchronous di raembu 16.

※ Note: The disclosure is based on the initial application.