KR970013115A - Method of manufacturing field effect transistor - Google Patents

Method of manufacturing field effect transistor Download PDF

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Publication number
KR970013115A
KR970013115A KR1019950025946A KR19950025946A KR970013115A KR 970013115 A KR970013115 A KR 970013115A KR 1019950025946 A KR1019950025946 A KR 1019950025946A KR 19950025946 A KR19950025946 A KR 19950025946A KR 970013115 A KR970013115 A KR 970013115A
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KR
South Korea
Prior art keywords
layer
photoresist
metal layer
gate
field effect
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Application number
KR1019950025946A
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Korean (ko)
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KR0151294B1 (en
Inventor
이원상
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구자홍
엘지전자 주식회사
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Priority to KR1019950025946A priority Critical patent/KR0151294B1/en
Publication of KR970013115A publication Critical patent/KR970013115A/en
Application granted granted Critical
Publication of KR0151294B1 publication Critical patent/KR0151294B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET

Abstract

본 발명은 전계효과트랜지스터 제조방법에 관한 것으로, 게이트를 フ 자형으로 제조하여 게이트 길이의 감소에 따른 저항의 증가를 방지하는데 적당하도록 한 것이다. 본 발명은 기판위에 PMMA층과 금속층 및 포토레지스트층을 차례로 적층시키는 단계와, 상기 포토레지스트를 선택적으로 노광 및 현상하여 게이트 형성부위를 디파인하는 단계, 노출되는 상기 금속층 부위를 각도를 준 건식식각에 의해 선택적으로 식각하는 단계, 상기 금속층의 제거된 부분의 상기 PMMA층 부위를 선택적으로 노광시키는 단계, 노출된 기판부위를 리세스 식각하는 단계, 기판상에 게이트 금속을 증착하는 단계, 및 상기 포토레지스트층을 리프트오프하고, 상기 금속층 및 PMMA층을 제거하는 단계를 포함하여 이루어지는 전계효과트랜지터 제조방법을 제공한다.The present invention relates to a method for manufacturing a field effect transistor, the gate is manufactured in a F-shape to be suitable for preventing the increase in resistance caused by the decrease in the gate length. The present invention comprises the steps of laminating a PMMA layer, a metal layer and a photoresist layer on the substrate in turn, and selectively exposing and developing the photoresist to fine-tune the gate forming region, the exposed metal layer portion to the angled dry etching Selectively etching, selectively exposing the PMMA layer portion of the removed portion of the metal layer, recess etching the exposed substrate portion, depositing a gate metal on the substrate, and the photoresist Lifting off the layer, and removing the metal layer and the PMMA layer provides a method for producing a field effect transistor.

Description

전계효과트랜지터 제조방법Field Effect Transistor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 GaAs 전계효과트랜지스터 제조방법을 도시한 공정 순서도3 is a process flowchart showing a GaAs field effect transistor manufacturing method according to the present invention.

Claims (4)

기판위에 PMMA층과 금속층 및 포토레지스트층을 차례로 적층시키는 단계와, 상기 포토레지스트를 선택적으로 노광 및 현상하여 게이트 형성부위를 디파인하는 단계, 노출되는 상기 금속층 부위를 각도를 준 건식식각에 의해 선택적으로 식각하는 단계, 상기 금속층이 제거된 부분의 상기 PMMA층 부위를 선택적으로 노광시키는 단계, 노출된 기판부위를 리세스 식각하는 단계, 기판상에 게이트 금속을 증착하는 단계, 및 상기 포토레지스트층을 리프트오프하고, 상기 금속층 및 PMMA층을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 전계효과트랜지스터 제조방법.Stacking a PMMA layer, a metal layer, and a photoresist layer on the substrate in turn, selectively exposing and developing the photoresist to define a gate forming portion, and selectively exposing the exposed metal layer portion by an angled dry etching. Etching, selectively exposing the PMMA layer portion of the portion where the metal layer has been removed, recess etching the exposed substrate portion, depositing a gate metal on the substrate, and lifting the photoresist layer Off, and removing the metal layer and the PMMA layer. 제1항에 있어서, 상기 포토레지스트층으로 1-라인용 포트레지스트를 사용하는 것을 특징으로 하는 전계효과트랜지스터 제조방법.The method of manufacturing a field effect transistor according to claim 1, wherein a one-line pot resist is used as the photoresist layer. 제1항에 있어서, 상기 게이트 형성부위의 디파인시 상기 포토레지스트의 폭은 0.5㎛ 정도로 하는 것을 특징으로 하는 전계효과트랜지스터 제조방법.The method of claim 1, wherein the width of the photoresist is about 0.5 μm when the gate is formed. 제1항에 있어서, 상기 금속층의 식각시 그 식각되는 폭은 0.4∼0.1㎛ 정도로 하는 것을 특징으로 하는 전계효과트랜지스터 제조방법.The method of claim 1, wherein the etching width of the metal layer is about 0.4 μm to about 0.1 μm.
KR1019950025946A 1995-08-22 1995-08-22 Method of fabricating field effect transistor KR0151294B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950025946A KR0151294B1 (en) 1995-08-22 1995-08-22 Method of fabricating field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950025946A KR0151294B1 (en) 1995-08-22 1995-08-22 Method of fabricating field effect transistor

Publications (2)

Publication Number Publication Date
KR970013115A true KR970013115A (en) 1997-03-29
KR0151294B1 KR0151294B1 (en) 1998-12-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950025946A KR0151294B1 (en) 1995-08-22 1995-08-22 Method of fabricating field effect transistor

Country Status (1)

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Also Published As

Publication number Publication date
KR0151294B1 (en) 1998-12-01

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