KR970008804B1 - Free set binary counter - Google Patents
Free set binary counter Download PDFInfo
- Publication number
- KR970008804B1 KR970008804B1 KR94028379A KR19940028379A KR970008804B1 KR 970008804 B1 KR970008804 B1 KR 970008804B1 KR 94028379 A KR94028379 A KR 94028379A KR 19940028379 A KR19940028379 A KR 19940028379A KR 970008804 B1 KR970008804 B1 KR 970008804B1
- Authority
- KR
- South Korea
- Prior art keywords
- binary counter
- set binary
- free set
- signals
- satisfying
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/665—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/48—Gating or clocking signals applied to all stages, i.e. synchronous counters with a base or radix other than a power of two
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Selective Calling Equipment (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
N flip-flops which is synchronized by a clock signal(CP), receives and latches the signals(D1,D2,...Dn), and outputs the output signals(Q1,Q2,...Qn); N carry lock ahead means for generating the output signals(A1,A2,...An), and satisfying the next logic equation; and N logic circuits for generating N signals(D1,D2,...Dn), and satisfying the next logic equation.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR94028379A KR970008804B1 (en) | 1994-10-31 | 1994-10-31 | Free set binary counter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR94028379A KR970008804B1 (en) | 1994-10-31 | 1994-10-31 | Free set binary counter |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960016143A KR960016143A (en) | 1996-05-22 |
KR970008804B1 true KR970008804B1 (en) | 1997-05-29 |
Family
ID=19396703
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR94028379A KR970008804B1 (en) | 1994-10-31 | 1994-10-31 | Free set binary counter |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970008804B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020049387A (en) * | 2000-12-19 | 2002-06-26 | 윤종용 | High speed counter having sequential binary order and the method thereof |
-
1994
- 1994-10-31 KR KR94028379A patent/KR970008804B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR960016143A (en) | 1996-05-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW357488B (en) | Glitch-free clock enable circuit and method for providing a glitch-free clock signal | |
ES2095932T3 (en) | PHASE SYNCHRONIZATION CIRCUIT FREQUENCY SYNTHESIZER WITH HARD LIMITER ACTIVATED BY A DIRECT DIGITAL SYNTHESIZER. | |
EP0967724A3 (en) | Calibrated delay locked loop for DDR SDRAM applications | |
EP0851581A3 (en) | Flip-flop circuit | |
ID26398A (en) | HIGH SPEED MULTIPLE MULTIPLICATION OF CML VLSI CIRCUITS | |
AU1082099A (en) | Method and apparatus for coupling signals between two circuits operating in different clock domains | |
US4475085A (en) | Clock synchronization signal generating circuit | |
US6507230B1 (en) | Clock generator having a deskewer | |
GB2353618A (en) | Multiple synthesizer based timing signal generation scheme | |
US4100541A (en) | High speed manchester encoder | |
KR970008804B1 (en) | Free set binary counter | |
EP0379279A2 (en) | Data transmission synchroniser | |
WO1996037954A3 (en) | Circuit for generating a demand-based gated clock | |
SE9301327D0 (en) | COMPOSED CLOCK SIGNAL | |
KR950029904A (en) | Clock signal generation method and apparatus | |
US4300232A (en) | Self synchronized multiplexer/demultiplexer | |
GB2227136A (en) | Frequency tracking system | |
SE9600726L (en) | Digital phase locked loop | |
US6236693B1 (en) | Generator for delay-matched clock and data signals | |
AU3114400A (en) | Low jitter high phase resolution pll-based timing recovery system | |
TW289883B (en) | Digital phase locked loop | |
KR100315702B1 (en) | Method for generating data clock and byte clock and apparatus therefor | |
KR930002256B1 (en) | Pcm clock generating circuit | |
RU1826077C (en) | Device for generation of time marks | |
KR960012943A (en) | Synchronous circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20060728 Year of fee payment: 10 |
|
LAPS | Lapse due to unpaid annual fee |