KR970007359B1 - Circuit for correcting error using hard decoder and soft decoder - Google Patents

Abstract

A error correction circuit using a hard decoder and soft decoder in order to improve the correction efficiency in the rapidly change channel situation whereby the hard deoder executes the error correction and the soft decoder executes the error/eraser correction.

Description

Error correction circuit using hard decoder and soft decoder

1 is a block diagram of a conventional error correction circuit.

2 is a block diagram of an error correction circuit using a hard decoder and a soft decoder according to a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

201: hard demodulator 203: error correction hard decoder

205: soft demodulator 207: error-erase correction software decoder

209: output determination unit

The present invention relates to an error correction circuit, and more particularly, to perform error correction through a hard decoder that performs error correction and a soft decoder that performs error-erasure correction, thereby improving error correction capability in a rapidly changing channel state. An error correction circuit using a soft decoder of a hard decoder.

Typically, as is well known in the art, an erasure and error correction soft decoder is about 3 dB better than a hard decoder that only performs error correction. However, this is possible under the premise that the optimal erasure area is used, and it is difficult to obtain this value in a system in which the state of the channel changes substantially.

1 shows a block diagram of a conventional error correction circuit as described above. As shown in the figure, the conventional error correction circuit includes a channel state estimator 10, a soft demodulator 20, and an error-erase decoder 30.

In FIG. 1, the estimator 10 estimates the channel state in the received signal on the channel. Here, the channel state includes a signal-to-noise ratio, a burst of noise, and the like.

On the other hand, the soft demodulator 20 is a digital signal ('0' and '1' in the case of binary) or erasure (erasure. Value not determined by any value) received from the channel state estimator 10; Make it. At this time, since the optimum value of the erasure area for making the erasure is a function of the channel state, the information obtained from the channel state estimator 10 is used.

The error-eraser correction decoding unit 30 restores the channel information received through an appropriate algorithm by using the eraser and the digital value output from the soft demodulator 20. In general, since the correction of the eraser is easier than the correction of the error, the performance of the soft decoder as described above is excellent.

However, the soft decoder as described above shows good performance when the optimal erasure area can be determined, but it is difficult to find the optimal value of the erasure area in a system in which the state of the channel changes rapidly, such as mobile communication. In addition, since estimation of the channel state requires complex hardware and software, not only the configuration is complicated but also the manufacturing cost increases.

The present invention is to solve the above problems of the prior art, by providing a soft decoder and a hard decoder to selectively output one output signal of the two decoders by using the number of erased, by simple hardware of the channel It is an object of the present invention to provide an error correction circuit using a hard decoder and a soft decoder that can increase error correction capability regardless of a change state.

In order to achieve the above object, the present invention provides hard demodulation-decoding means for detecting an error in a received signal, correcting the detected error, and restoring channel information, and making the received signal a digital value or an eraser. And the soft demodulation-decoding means for restoring the channel information by the digital value, the output of the hard demodulation-decoding means and the output of the soft demodulation decoding means based on the erased number signal from the soft demodulation-decoding means. An error correction circuit using a hard decoder and a soft decoder comprising output determination means for outputting selectively is provided. Further, in the error correction circuit of the present invention as described above, the hard demodulation-decoding means and the soft demodulation-decoding means are connected in parallel to each other, and are configured to simultaneously demodulate-decode the same input signal.

Hereinafter, a preferred embodiment of an error correction circuit using a hard decoder and a soft decoder according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an error correction circuit using a hard decoder and a soft decoder according to an embodiment of the present invention. As shown in the figure, the error correction circuit of the present invention comprises a hard demodulator 201, an error correction hard decoder 203, a soft decoder 205, an error-eraser correcting soft decoder 207, and an output decision unit. 209.

Referring to FIG. 2, an error correction hard decoder 203 is connected to a hard demodulator 201 that detects an error in a received signal, and the received signal is converted into a digital value or an eraser. In the soft demodulator 205, an error-erase correcting software decoder 207 for restoring channel information sent through an appropriate algorithm is provided by using an eraser and a digital value output from the soft demodulator 205. Connected.

The error correction hard decoding unit 203 and the error-erase correction soft decoding unit 207 are connected to an output determination unit 209 which selects and outputs one of the outputs of the two decoding units.

In this case, the number of erased output lines output from the error-erase correction soft decoding unit 207 are connected to the selection signal terminal of the output determination unit 209.

Next, the error correction operation procedure of the present invention as described above will be described.

First, the received signal is recovered to the channel report by correcting the error detected by the error correction hard decoder 203 after the error is detected through the hard demodulator 201.

At the same time, the signal received through the soft demodulator 205 becomes a digital value or an eraser. The error-eraser corrected soft decoder 209 receives the received eraser and the digital value through an appropriate algorithm. Channel information is restored.

On the other hand, in the output determination unit 209, the error correction hard decoder 203 and the error-erase correction soft decoder (203) based on the erased number from the error-erase corrected software decoder 207. One of the outputs of 207 is selected.

That is, in the output determining unit 209, if the number of erased outputs from the error-erase correcting software decoding unit 207 falls within the maximum eraser correcting capability of the error-erase correcting software decoding unit 207, the error- The output of the error correction hard decoding unit 203 is selected when the output of the erasure correction software decoding unit 207 is selected and the number of erased numbers exceeds the maximum erase correcting capability of the error-erase correction software decoding unit 207. Is selected.

Here, if the error erasure correction software decoding section 207 exceeds the maximum eraser correction capability, the eraser region is wrong and becomes a region that is not as good as the error correction hard decoder 203, so that the error correction hard decoder ( The signal output from 203 is selected.

Therefore, even if the state of the channel changes drastically through the above-described process according to the present invention, better error correction performance can be obtained without a complicated channel structure and an expensive channel estimation circuit.

As described above, according to the present invention, by connecting the soft decoder and the hard decoder in parallel with each other and selecting and outputting one of the outputs of the two decoders by using the erased numbers, the complex channel state estimation provided in the above-described prior art. This eliminates the need for circuitry and simplifies hardware and software, reducing manufacturing costs and improving the performance of the overall system by increasing the correction capability in systems with rapidly changing channel conditions such as mobile wireless communications. have.

Claims (2)

Hard demodulation-decoding means for detecting an error in the received signal and correcting the detected error to restore channel information; Soft demodulation-decoding means for converting the received signal into a digital value or an erasure and then restoring channel information by the erasure and the digital value; Using a hard decoder and a soft decoder comprising output determination means for selectively outputting the output of the hard demodulation-decoding means and the output of the soft demodulation-decoding means based on the erased number signal from the soft demodulation-decoding means. Error correction circuit. 2. The error correction circuit according to claim 1, wherein the hard demodulation-decoding means and the soft demodulation-decoding means are connected in parallel to each other and simultaneously demodulate-decode the same input signal.