KR970005037Y1 - Gate allay for i/o card of plc - Google Patents

Abstract

None.

Description

PLC's Gate Array

1 is a block diagram of a conventional IC card gate array.

2 is a gate array block diagram of an input / output card of the present invention PLC.

3 is a detailed view of the first output drive reversal in FIG.

* Explanation of symbols for main parts of the drawings

201: data buffer section 202: data selection section

203: data transfer unit 204: output drive inverting unit

204a: first output driver relay 204b: second output driver relay

204c: third output driver relay 204d: fourth output driver relay

205: selection signal generator 206: clock generator

207: output enable unit MUX7: main multiplexer

The present invention relates to a gate array for an input / output card of a PLC (PLC: Programmable Logic Controller). Especially, 8-bit data and 16-bit data can be stored for a PLC with a simple mode setting without a large increase in mounting space. The present invention relates to a gate array for PLC's input / output card capable of inputting / outputting.

In general, 'PLC's input / output card gate array' is a gate array used for PLC's I / O card. When data is written, the data is input from outside. When the data is read and read, it refers to a device that transmits the data of the PL to the outside. The gate array for the I / O card of the PL is used for 8-bit data according to the data management method of the PL. It is for 16-bit data.

FIG. 1 shows a block diagram of a conventional PLC IC gate array (for 8-bit data). When data is written, 8-bit data (XDO-XD7) input from the outside is transferred, and data is written. The first bidirectional buffer (IOBU1) for outputting the 8-bit data input from the PLC (not shown) to the outside; First to fourth flip-flops DFF1 to DFF4 for transferring 32-bit data of 8-bit data XDO-XD7 from the outside transferred by the first bidirectional buffer IOBU1 by 8 bits. and; The second bit which writes the 32-bit data transmitted by the first dip-flop (DFF1) to the fourth dip-flop (DFF4) to the PLC when data is written, and the 32-bit data of the PLC when the data is read. A bidirectional buffer IOBU2; The first buffer BIFF1 to the fourth buffer BUFF4 input 32-bit data transmitted by the second bidirectional buffer IOBU2 to the first bidirectional buffer IOBU1 by 8 bits.

The operation of the conventional PLC input / output card gate array having such a configuration will be described.

When writing data of the PLC, the first bidirectional buffer IOBU1 receives the 8-bit data XDO-XD7 to be written from the outside and inputs it to the first flip-flop DFF1 to the fourth flip-flop DFF4. do.

The first deflected flop DFF1 to the fourth deflected flop DFF4 output 8 bit data XDO-XD7 inputted from the first bidirectional buffer IOBU1 through the output port Q in total. The bit data is input to the second bidirectional buffer IOBU2.

The second bidirectional buffer IOBU2 writes the received 32-bit data to the PLC.

In the case of reading the data of PLC, the second bidirectional buffer IOBU2 receives 32 bits of data from the PLC and transmits the first bidirectional buffer (8) through the first buffer BUFF1 to the fourth buffer BFF4 by 8 bits. When input to IOBU1, the first bidirectional buffer IOBU1 outputs the received 8-bit data to the outside.

The problem with the conventional PLC IC gate array having such a configuration and operation is that only 8-bit data (or 16-bit data) is input and output to the PLC. In order to input and output, a 16-bit data (or 8-bit data) gate array must be additionally provided, and it is designed not to input / output by inverting data. As a result, the mounting space is greatly increased.

The present invention has been devised in view of the problems of the conventional PL array of input and output cards.

It is an object of the present invention to provide a gate array for a PLC input / output card capable of inputting and outputting both 8-bit data and 16-bit data to the PLC with a simple mode setting without a large increase in the mounting space.

Another object of the present invention is to provide a gate array for PLC's input / output card that can input and output by inverting data without a large increase in mounting space.

The gate array for the input / output card of the present invention according to the above object is a selection signal generator for outputting a data selection signal and a buffer enable signal according to an address signal input from the outside, and a bit selection signal input from the outside. In the bit data mode, a data selector for selecting 8-bit data from the outside and 16-bit data from the external in the 16-bit data mode, and a clock generation for generating a clock signal according to the data select signal of the select signal generator. Wealth; A data transfer unit transferring 8-bit data or 16-bit data input from the outside or selected by the data selection unit according to the clock signal of the clock generation unit; An output enable section for generating an output enable signal; 8-bit data or 16-bit data transmitted by the data transfer unit is written to the PLC according to the inversion signal input from the outside during data writing and the output enable signal of the output enable unit. An output driving inverting unit for transferring data or 16-bit data as it is or inverted according to the inversion signal; A main multiplexer for selecting any one of 8-bit data and 16-bit data transmitted by the output driver inverting unit according to the data selection signal and the inversion signal of the selection signal generator, and 8-bit selected by the main multiplexer It is composed of a data buffer unit for outputting data or 16-bit data to the outside.

The operation and effects of the present invention will be described in detail with reference to FIGS. 2 and 3 showing one specific embodiment of the PL array of the present invention.

In this specific embodiment, the data buffer portion of the gate array for the input / output card of the present invention is composed of the first bidirectional buffer IOBU1 and the second bidirectional buffer IOBU2, as indicated by reference numeral 201 in FIG. The parallel structure includes an AND gate AND1 having an output side connected to the enable terminal G of the second bidirectional buffer IOBU2, and a sickgate NOT connected to one input terminal of the AND gate AND1.

As shown by reference numeral '202', the data selection unit receives 4-bit data from the outside through the first and second input ports A and B and according to the bit selection signal Bit_S input from the outside. Composed of the first multiplexer (MUX1) to the fourth multiplexer (MUX4) to select any one of the first, second input port (A), (B) to output through each output port (Y) do.

As shown by reference numeral 203, the data transfer unit outputs the data input through the data input terminal D according to the input clock signals CK1-CK4. It consists of a flop (DFF4).

At this time, the first deflected flop DFF1 to the fourth deflected flop DFF4 are cleared according to the reset signal RST input from the outside to the clear terminal CLR.

As shown by the reference numeral '204', the output driving inverting unit causes the data inputted from the data transfer unit 203 at the time of data writing to be intact or spotted according to the inversion signals INVO and INV1 inputted from the outside. The first output driver 204a to the fourth output driver 204d that writes to the PLC (not shown) and inputs the PLC data to the main multiplexer MUX7 as it is or inverted when the data is read. It consists of.

The clock generation unit receives a plurality of data selection signals from the selection signal generation unit 205 and selects the data selection signals according to the bit selection signal Bit_S input from the outside, as indicated by reference numeral 206. Multiplexer (MUX5); One side is connected to an output side of the fifth multiplexer MUX5, and the other side is configured as an oragate OR to which an enable signal WR_, which is a light from the outside, is input.

As shown by reference numeral 207, the output enable portion is connected to the AND gate AND2 and the output of the AND gate AND2 which AND-combines the bit selection signal Bit_S and the 1-bit data XD14 from the outside. And a sixth multiplexer MUX6 that selects one of the data XD10-XD13 input from the outside and the output enable signal out_ENO, 1 to generate the output enable signal out_ENO-out_EN3. .

In this case, 'CS-' input to the selection signal generator 205 or the main multiplexer MUX7 is a chip selection signal, and 'STB' is an enable signal used when two gate arrays are used in parallel. 'A0-A3' is an address signal and 'XD15' is input data.

In this configuration, a case of writing the 8-bit data and 16-bit data from the outside to the PLC will be described first.

When data is written to the PLC, the low-order 8-bit data (XD0-XD7) and the high-order 8-bit data (XD8-XD15) to be written to the PLC are input from the outside, and the low-order 8-bit data (XD0-XD7) is inputted. The lower 4 bit data of XD0-XD13 is input to the first input port 4 of the first, third multiplexer (MUX1) and the (MUX3) of the data selector 202 and the upper 4 bit data (XD4). -XD7 is input to the first input port 4 of the second, fourth multiplexer MUX2, and MUX4 of the data selector 20.

The lower 4-bit data XD8-XD11 of the upper 8-bit data XD8-XD15 are input to the second input port B of the first, third multiplexer MUX1, MUX3, and higher. The 4-bit data XD12-XD15 are input to the second input port B of the second, fourth multiplexer MUX2, and MUX3.

Hereinafter, the 8-bit data mode and the 16-bit data mode will be described separately.

In the case of 8-bit data collection, the bit selection signal Bit_s input from the outside of the gate array for the input / output card of PLC and input to the selection signal generation unit 205, the data selection unit 202, etc. becomes 'low'.

As the bit select signal Bit_s becomes 'low' as described above, the first multiplexer MUX1 of the data selector 202 receives the lower four-bit data XD0-XD3 input to the first input port A. FIG. Is selected, the second multiplexer (MUX2) selects the upper 4-bit data (XD4-XD7) input to the first input port (A), and the third multiplexer (MUX3) is the first input port (AUX). ) Selects the lower 4-bit data (XD0-XD3) and the fourth multiplexer (MUX4) selects the upper 4-bit data (XD4-XD7) input to the first input port (A).

With this selection, the lower four-bit data XD0-XD3 and the upper four-bit data XD4 output from the output port Y of the first, second multiplexer MUX1, and MUX2 of the data selection unit 202. -XD7) are combined into 8-bit data (XD0-XD7) and input to the data input terminal (D) of the second flip-flop (DFF2) of the data transfer unit (203). The lower 4-bit data (XD0-XD3) and the upper 4-bit data (XD4-XD7) output from the output port (Y) of the fourth multiplexer (MUX3) and (MUX4) are also 8-bit data (XD0-XD7). The data input terminal D is input to the data input terminal D of the fourth flip-flop DFF4 of the data transfer unit 203.

At this time, the lower 8-bit data (XD0-XD7) from the outside is included in the data input terminal (D) of the first and second flip-flops (DFF1) and (DFF3) of the data transfer unit (203). It is input directly without passing through 202.

On the other hand, the selection signal generator 205 generates one of the data selection signals DECO0-4 and 6 according to the three address signals A0-A2 input from the outside of the gate array for the input / output card of PL. The data selection signal DECO0, the data selection signal DECO2, the data selection signal DECO4, or the data selection signal DECO6 are input to the first input port A of the fifth multiplexer MUX5 of the clock generator. The data selection signal DECO0 or the data selection signal DECO2 is input to the second input port B of the fifth multiplexer MUX5.

As described above, the fifth multiplexer MUX5 of the clock generator 206 selects the first input port A and selects the first input port A because the bit select signal Bit_s is 'low'. The clock signal is output in accordance with the data selection signal input to A).

That is, when the data selection signal DECO0 is input to the first input port A, the fifth multiplexer MUX5 outputs the first click signal CK1 through the output port Y to generate an oragate ( OR is input to the clock terminal CLK of the first dip-flop DFF1 of the data transfer unit 203.

At this time, the OR gate OR combines the write enable signal WR_ from the outside with the output of the fifth multiplexer MUX5.

The first flip-flop DFF1 of the data transfer unit 203 receiving the first clock signal CK1 outputs the lower 8-bit data XD0-XD7 input to the data input terminal D. Output through and input to the first output drive inverter 204a of the output drive inverter 204.

The first output driver reversal 204a, which has received the lower 8-bit data XD0-XD7, outputs the lower 8-bit data XD0-XD7 as it is or inverted and writes the data to PLC.

That is, referring to FIG. 3 showing a detailed block of the first output driver relay 204a, one bit data XD0 of the input lower 8-bit data XD0-XD7 is the first output driver relay 204a. Is output through the first exclusive or gate (XOR1) and the three-state buffer (B1) of the) and is written to the PLC, wherein the output enable signal (out_ENO) input to the three-state buffer (B1) is 'high' The inversion signal INVO input to one input terminal of the first exclusive or gate XOR1 should be 'low'.

If the 1-bit data XD0 is to be inverted and written to the PLC, the inversion signal INVO may be set to 'high'. Accordingly, the exclusive exclusive operation is performed on the first exclusive oragate XOR1. The 1-bit data XD0 is inverted and written to the PLC through the tri-state buffer B1.

Other 1-bit data among the lower 8-bit data XD0-XD7 are also inverted or inverted according to the level of the inversion signal INVO while the output enable signal out_ENO is high, similarly to the 1-bit data XD0. Then it is written to PI.

On the other hand, if the data selection signal DECO2 is input to the first input port A of the fifth multiplexer MUX5 of the clock generator 206, the fifth multiplexer MUX5 is the output port Y. The second clock signal CK2 is output through the input signal, and is input to the clock terminal CLK of the second flip-flop DFF2 of the data transfer unit 203 through the OR gate OR.

The second flip-flop DFF2 input to the data transfer unit D receiving the second clock signal CK2 is connected to the data input terminal D from the first and second multiplexer MUX1 and MUX2. ) And outputs the lower 8-bit data XD0-XD7 inputted through the output terminal Q and inputs it to the second output drive inverter 204b of the output drive inverter 204.

Although not shown in FIG. 3 for convenience, the second output driver 204b having the same configuration as the first output driver 204a is similar to that of the first output driver 204a. If the version signal INVO is low, the signal is output as it is and written to the PLC.

On the other hand, when the data selection signal DECO4 or the data selection signal DECO6 is input to the first input port A of the fifth multiplexer MUX5 of the clock generation unit 206, the clock generation unit ( 206, the operations of the data transfer unit 203 and the output drive inverting unit 204 are the same as in the case where the data selection signal DECO0 or the data selection signal DEXO2 has been previously input.

Next, a case where the data of the PLC is read and output to the outside in the 8-bit data mode will be described.

When the PLC data is read out and output to the outside, PLC's 8-bit data (XIO0-XIO7), (XIO8-XIO15), (XIO16-XIO23), and (XIO24-XIO31) are output drive inverting units 204. Is entered.

That is, the 8-bit data (XIO0-XIO7) of PLC is inputted to the first output drive inverter 204a of the output drive inverter 204.

Referring to FIG. 3, the first output driver inverting unit 204a receiving 8-bit data (XIO0-XIO7) receives a second exclusive oragate of 1-bit data (XIO0) among the 8-bit data (XIO0-XIO7). When the inversion signal INVO is 'low', it is input as it is to the main multiplexer MUX7, and when the inversion signal INVO is 'high', the signal is inverted. Enter in flexure (MUX7).

The other 1-bit data among other 8-bit data (XIO0-XIO7) is the same as the case of the 1-bit data (XIO0) above.

The 8-bit data of the PLC (XIO8-XIO15) is inputted to the second output drive inverter 204b of the output drive reversing unit 204, and the 8-bit data of the PLC (XIO16-XIO23) is output drive board. The third output driver relay 204c of the whole 204 is inputted, and the 8-bit data of PLC (XIO24-XIO31) are respectively input to the fourth output driver relay 204d of the output driver inverter 204. The 8-bit data is input to the main multiplexer MUX7 as in the case of (XIO0-XIO7).

The main multiplexer (MUX7) receiving 8-bit data (XIO0-XIO7), (XIO8-XIO15), (XIO16-XIO23), and (XIO24-XIO31) receives the data selection signal input from the selection signal generator 205. 8-bit data (XIO0-) input from the first output drive inverter 204a of the output drive inverter 204 according to (DECO0, 2, 4, 6) and the inversion signal INVO.1 input from the outside. XIO7 is selected and output through the first output port Y and input to the first bidirectional buffer IOBU1 of the data buffer unit 201.

The 8-bit data of PLC (XIO0-XIO7) receives the first two-way buffer IOBU1 of the data buffer unit 201, which is a buffer of 'high' inputted from the selection signal generator 205, the signal BB_EN_. Since 8-bit data (XIO0-XIO7) is output through the output port (Y) to the outside, the read operation is completed.

At this time, since the bit select signal Bit_S is 'low' (because of the 8-bit mode), the second bidirectional buffer IOBU2 is in a disabled state.

That is, the bit select signal Bit_S that is low is inverted by the not gate NOT and becomes high, and this and the high buffer enable signal BF_EN_ are AND-combined with the AND gate AND1, so that the high signal is finally zeroed. Since it is input to the enable terminal G of the two-way buffer IOBU2, the second two-way buffer IOBU2 is disabled.

Now, in the 16-bit data mode, the external data is written to PLC.

In the case of the 16-bit data mode, the bit selection signal Bit_S input from the outside of the gate array for the PIC input / output card is 'high' as opposed to the case of the 8-bit data mode.

Accordingly, the first multiplexer MUX1 of the data selector 202 selects the lower 4 bit data XD8-XD11 of the upper 8 bit data XD8-XD15 input to the second input port B. FIG. The second multiplexer MUX2 selects the upper 4 bit data XD12-XD15 of the upper 8 bit data XD8-XD15 input to the second input port B, and the third multiplexer MUX2. The MUX3 selects the lower 4-bit data XD8-XD11 of the upper 8-bit data XD8-XD15 input to the second input port B, and the fourth multiplexer MUX4 selects the second input port B. The upper 4-bit data XD12-XD15 of the upper 8-bit data XD8-XD15 inputted to B) is selected.

By this selection, the lower 4-bit data (XD8-XD11) and the upper 4-bit data (XD12-XD15) respectively output from the output ports Y of the first and second multiplexers MUX1 and MUX2 are combined. The 8-bit data XD8-XD15 are input to the data input terminal D of the second flip-flop DFF2 of the data transfer unit 203, and the third and fourth multiplexers MUX3 and MUX4. The lower 4 bit data (XD8-XD11) and the upper 4 bit data (XD12-XD15) respectively output from the output port (Y) of the N1 are combined to become 8 bit data (XD8-XD15). The data is input to the data input terminal D of the fourth flip-flop DFF4.

The lower 8-bit data XD0-XD7 from the outside is directly input to the data input terminal D of the first flip-flop DFF1 and the third flip-flop DFF3 of the data transfer unit 203. .

At this time, the selection signal generator 205 receives the data selection signal DECO0 or the data selection signal DECO2 generated according to the three address signals A0-A2 input from the outside of the gate array for the input / output card of PL. It is input to the second input port B of the fifth multiplexer MUX5 of the clock generator 206.

At this time, as described above, the fifth multiplexer MUX5 of the clock generator 206 selects the second input port B and selects the second input because the bit select signal Bit_S is 'high'. When the data selection signal DECO0 is input to the port B, the first and second clock signals CK1 and CK2 are output through the output port Y to transmit the data through the oragate OR. Inputs are made to clock terminals CLK of the first and second flip-flops DFF1 and DFF2 of 203, respectively.

The first flip-flop DFF1 of the data transfer unit 203 receiving the first clock signal CK1 outputs the lower 8-bit data XD0-XD7 input to the data input terminal D. The second deflip flop DFF2 of the data transfer unit 203 which is output through the first output drive inverter 204a of the output drive inverter 204 and at the same time receives the second clock signal CK2. ) Outputs the upper 8-bit data (XD8-XD15) input to the data input terminal (D) through the output terminal (Q) and inputs it to the second output driving relay (204b) of the output driving inverter (204). .

The first and second output driver relays 204a and 204b operate in the same manner as in the 8-bit data mode. When the inversion signal INVO input from the outside is 'low', the 8-bit data XD0 is input. -XD7), (XD8-XD15) and 16-bit data (XD0-XD15) are output as it is and written to PLC, and 16-bit data (XD0-XD15) input when the inversion signal (INVO) is 'high'. Invert the output and write it to PI.

On the other hand, when the data selection signal DECO2 is input to the second input port B of the fifth multiplexer MUX5 of the clock generator 206, the fifth multiplexer MUX5 is configured to be the third and the third. The fourth clock signal CK3 and CK4 are output to output the third clock signals CK3 and CK4 so that the third clock signal CK3 is the third dip flip-flop DFF3 of the data transfer unit 203. The fourth clock signal CK4 is input to the fourth flip-flop DFF4 of the data transfer unit 203.

Accordingly, the 8-bit data XD0-XD7 input to the third flip-flop DFF3 and the 8-bit data XD8-XD15 input to the fourth deflip-flop DFF4 have been previously described. Similar to the 8-bit data XD0-XD7 and XD8-XD15 inputted to the flip-flops DFF1 and DFF2, they are written in or out of the output drive inverting unit 204 as they are or are inverted.

Next, the PLC data is read and output to the outside in the 16-bit data mode.

When the 16-bit data of the PLC is read, the 16-bit data of the PLC is input to the output drive inverting unit 204.

That is, the lower 8-bit data of PLC (XIO0-XIO7) is inputted to the first output drive inverter 204a of the output drive inverter 204, and the upper 8-bit data of PLC is (XIO8-XIO15). Is input to the second output drive inverter 204b of the output drive inverter 204.

The first output drive relay 204a receiving the lower 8-bit data (XIO0-XIO7) from the PLC is second exclusive of the 1-bit data (XIO0) among the lower 8-bit data (SIO0-XIO7) in FIG. When the inversion signal INVO is 'low', the input signal is input to the main multiplexer MUX7 as it is, and when the inversion signal INVO is 'high', the signal is inverted when the inversion signal INVO is 'high'. Enter in flexure (MUX7).

The same is true for other 1-bit data.

The second output driver 204b, which has received the upper 8 bit data (XIO8-XIO15) from the PLC, also holds the upper 8 bit data (XIO0-XIO15) as it is or the first output driver 204a. Invert it and input it to the main multiplexer (MUX7).

Meanwhile, other lower 8-bit data (XIO8-XIO15) of the PLC are inputted to the third output drive inverter 204c of the output driving inverting unit 204, and the other upper 8-bit data (XIO24-XIO31) of the PLC. Is input to the fourth output driver reversal 204d of the output driver reversal unit 204, and the main multiplexer (XIO8-XIO15) is the same as in the case of the lower 8-bit data (XIO0-XIO7) and the upper 8-bit data (XIO8-XIO15). MUX7).

The main multiplexer (MUX7), which has received 8 bits of data (XIO0-XIO7), (XIO8-XIO15), (XIO16-XIO23), and (XIO24-XIO31) of PL, is input from the selection signal generator 205. Lower 8-bit data input from the first output drive inverter 204a of the output drive inverter 204 in accordance with the data selection signal DECO0.2 * 2 and the inversion signal INVO.1 input from the outside. (XIO0-XIO7) is selected and output through the first output port (Y1) and input to the first bidirectional buffer (IOBU1) of the data buffer unit 201, the upper input input from the second output drive relay 204b The 8-bit data XIO8-XIO15 are selected and output through the second output port Y2 and input to the second bidirectional buffer IOBU2 of the data buffer unit 201.

The first bidirectional buffer IOBU1 of the data buffer unit 201 that receives the lower 8-bit data (XIO0-XIO7) of the PLC is 'high' buffer enable signal BF_EN_ input from the selection signal generator 205. Since the 8-bit data (XIO0-XIO7) is output to the outside through the output port (Y), and the upper 8-bit data (XIO8-XIO15) of PLC receives the The second two-way buffer IOBU2 is enabled by the 'high' buffer enable signal BF_EN_ and the bit selection signal Bit_S input from the selection signal generator 205, so that the upper eight bits of data IOOB-XIO15 are used. ) To the outside through the output port (Y) to complete the read operation.

As described in detail above, the P / C gate array of the present invention can input and output both 8-bit data and 16-bit data to the PLC by simple mode setting, and thus, separate 16-bit (or 8-bit). There is no need to provide a data gate array, and the output drive inverter of the present invention can invert and input 8-bit data or 16-bit data with respect to PLC, so there is no need for a separate inversion device. The mounting space of Mr. I / O card is greatly reduced.

Claims (3)

A selection signal generator for outputting a data selection signal and a buffer enable signal according to an address signal input from the outside; A data selection unit for selecting 8-bit data from the outside in the 8-bit data mode and 16-bit data from the outside in the 16-bit data mode according to a bit selection signal input from the outside; A clock generator which generates a clock signal according to the data selection signal of the selection signal generator; A data transfer unit transferring 8-bit data input from the outside or 8-bit data or 16-bit data selected by the data selector according to a clock signal of the clock generator; An output enable section for generating an output enable signal; 8-bit data or 16-bit data transmitted by the data transfer unit is written to the PLC according to the inversion signal input from the outside during data writing and the output enable signal of the output enable unit. An output driving inverting unit for transferring data or 16-bit data as it is or inverted according to the inversion signal; A main multiplexer for selecting either 8-bit data or 16-bit data transmitted by the output driver inverting unit according to the data selection signal and the inversion signal of the selection signal generator; And a data buffer for outputting 8-bit data or 16-bit data selected by the main multiplexer to the outside. 2. The PLC of claim 1, wherein the output driver inverting unit includes first to fourth output driver inverters for transmitting 8-bit data inputted as it is or inverted according to the inversion signal. Gate array for input and output cards. The eighth exclusive OR of claim 2, wherein the first to fourth output driver relays each perform exclusive or logical operations on the 1-bit data input from the data transfer and the inversion signal. Eight tri-state buffers respectively delivering the gates and the outputs of the eight first exclusive oar gates according to the output enable signals of the output enable unit, and exclusively for one bit data of the PLC and the inversion signal. 8. A gate array for an input / output card of a PLC, comprising eight second exclusive oragates for performing oan logic operations.