KR970004336A - Address input buffer - Google Patents

Address input buffer Download PDF

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Publication number
KR970004336A
KR970004336A KR1019950016028A KR19950016028A KR970004336A KR 970004336 A KR970004336 A KR 970004336A KR 1019950016028 A KR1019950016028 A KR 1019950016028A KR 19950016028 A KR19950016028 A KR 19950016028A KR 970004336 A KR970004336 A KR 970004336A
Authority
KR
South Korea
Prior art keywords
input buffer
address
outside
address input
bit register
Prior art date
Application number
KR1019950016028A
Other languages
Korean (ko)
Inventor
이재진
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950016028A priority Critical patent/KR970004336A/en
Publication of KR970004336A publication Critical patent/KR970004336A/en

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Abstract

본 발명의 어드레스 입력 버퍼는 정상상태에서는 외부로부터의 어드레스 신호를 그대로 출력라인상으로 전송하고 대기상태에서는 이전 정상상태에서의 어드레스를 기억함으로써, 동일한 어드레스 신호가 연속적으로 입력될 경우에는 전력소모양을 줄이는 잇점을 제공한다. 이를 위하여, 본 발명의 어드레스 입력 버퍼는 외부로부터의 제어신호에 따라 외부로부터의 어드레스 신호를 출력라인상으로 그대로 공급하거나 일정시간 기억하는 1비트 레지스터와, 상기 제어신호에 따라 외부로부터의 어드레스 신호를 상기 1비트 레지스터쪽으로 절환하는 절환부를 구비한다.The address input buffer of the present invention transmits address signals from the outside as they are on the output line in the normal state and stores the addresses in the previous normal state in the standby state, thereby reducing the power consumption when the same address signals are continuously input. It provides an advantage. To this end, the address input buffer of the present invention is a 1-bit register for supplying the address signal from the outside as it is on the output line or storing it for a predetermined time, and the address signal from the outside according to the control signal. And a switching unit for switching to the one-bit register.

Description

어드레스 입력 버퍼Address input buffer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 실시예에 따른 어드레스 입력 버퍼를 도시한 회로도.3 is a circuit diagram illustrating an address input buffer according to an embodiment of the present invention.

Claims (3)

외부로부터의 제어신호에 따라 외부로부터의 어드레스 신호를 출력라인상으로 그대로 공급하는 동시에 일정시간 저장하는 1비트 레지스터와, 상기 제어신호에 따라 외부로부터의 어드레스 신호를 상기 1비트 레지스터쪽으로 절환하는 절환수단을 구비한 것을 특징으로 하는 어드레스 입력 버퍼.A 1-bit register for supplying the address signal from the outside as it is on the output line and storing it for a predetermined time according to a control signal from the outside, and switching means for switching the address signal from the outside to the 1-bit register according to the control signal. Address input buffer, characterized in that provided. 제1항에 있어서, 상기 1비트 레지스터가 두개의 NAND 게이트로 구성된 것을 특징으로 하는 어드레스 입력 버퍼.2. The address input buffer of claim 1 wherein said one bit register consists of two NAND gates. 제1항에 있어서, 상기 절환수단이 NAND 게이트인 것을 특징으로 하는 어드레스 입력 버퍼.The address input buffer according to claim 1, wherein said switching means is a NAND gate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950016028A 1995-06-16 1995-06-16 Address input buffer KR970004336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950016028A KR970004336A (en) 1995-06-16 1995-06-16 Address input buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950016028A KR970004336A (en) 1995-06-16 1995-06-16 Address input buffer

Publications (1)

Publication Number Publication Date
KR970004336A true KR970004336A (en) 1997-01-29

Family

ID=66524495

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950016028A KR970004336A (en) 1995-06-16 1995-06-16 Address input buffer

Country Status (1)

Country Link
KR (1) KR970004336A (en)

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