KR970003797B1 - Encoding method for video bit stream - Google Patents

Abstract

A video bit stream encoding method adds I picture start address(ISPA) information to a video GOP(Group of Picture) layer, constructs MPEG I video bit stream, thereby achieving a high-speed reproducing at a receiving terminal. The video bit stream encoding method includes the steps of: if the input picture is I picture, subtracting a present I picture start address from a previous I picture start address. and calculating I picture start address; storing a start address of the present picture; and encoding I picture start address after encoding a picture type. When the multiplexer performs an encoding about GOP layer, the above steps are performed, and a predetermined video bit stream is loaded.

Description

Video bit stream encoding method

1 is a block diagram showing a conventional bit stream encoding circuit.

2 is a block diagram for performing a video bit stream encoding method according to the present invention.

3 is a flowchart for performing a video bit stream encoding method according to the present invention.

* Description of the symbols for the main parts of the drawings *

101: frame rearrangement unit 102: motion estimation unit

103: subtractor 104: discrete cosine transform unit

105: quantization unit 106: variable length encoding unit

107: multiplexer 108: transmission buffer

109 regulator 110 inverse quantization unit

111: inverse discrete cosine transform unit 112: adder

113: frame storage and prediction unit 115: IPSA calculation and encoder

The present invention relates to a video bit stream encoding method, and more specifically, to a video group of picture (GOP) layer, information about an I picture start address (hereinafter referred to as ISPA) is added to MPEG ( Moving Picture Experts Group) The present invention relates to a video bit stream encoding method in which high-speed playback is possible at a receiving end by constructing a video bit stream.

1 is a block diagram of a conventional bit stream encoding circuit.

1 is a frame rearranging unit 101 for rearranging an input original picture, and a motion estimating unit estimating how far the frame data rearranged in the frame rearranging unit 101 has moved relative to a previous frame ( Motion Estimation 102, a subtractor 103 for outputting a difference signal between frames by subtracting a predicted image signal between frames whose motion is compensated from the output signal of the motion estimator 102, and outputting the output of the subtractor 103. DCT unit 104 for discrete cosine transform (hereinafter referred to as DCT) in a form that is easy to compress, a quantization unit 105 for quantizing the output of the DCT 104, and the quantization unit 105 Variable length code (hereinafter referred to as VLC) section 106 for converting the output into appropriate variable length code data (code word), mode and vector output from the motion estimation section 102, and the VLC. During output of negative 106 The multiplexer 107 which selects and outputs me, the transmission buffer 108 temporarily storing the output of the multiplexer 107 for transmission as bit stream data, and the output of the transmission buffer 108 are normalized to quantize the quantization parameter. A regulator 109 outputting to the unit 105, an inverse quantizer 110 for quantizing the output of the quantization unit 105, and an inverse DCT unit for inverse discrete cosine-converting the output of the inverse quantization unit 110 ( 111, an adder 112 for adding a predictive image signal between the output of the inverse DCT unit 111 and a frame whose motion is compensated for, a delay of the output of the adder 112 for a predetermined frame time, and the motion estimating unit ( The frame storage and prediction unit 113, which removes visual errors due to the movement, by the output of the adder 112 and the output of the adder 112, and a picture starting address address are coated to output as a selection signal of the multiplexer 107. Coating consists of a start address 114.

In FIG. 1 configured as described above, the input original picture is rearranged in the frame rearranging unit 101 and estimated in which direction how much the frame data rearranged in the motion estimating unit 102 has moved compared to the previous frame. The subtractor 103 is output to the multiplexer 107 and the frame storage and predictor 113.

At this time, the subtractor 103 subtracts the predicted image signal between the signal whose motion is estimated and the frame whose motion is compensated by the frame storage and predicting unit 113, and outputs a difference signal between the frames.

The output of the subtractor 103 is discrete cosine transformed to remove spatial redundancy in the DCT 104 and then input to the quantizer 105.

The quantization unit 105 maps consecutive values output from the DCT unit 104 to discontinuous values and provides them to the VLC unit 106.

In order to remove redundancy of the data bit stream itself, the VLC unit 106 allocates a code value having a high frequency and a code value having a low frequency to a large code value and outputs the result to the transmission buffer 108 through the multiplexer 107. do. In this case, the output of the transmission buffer 108 provides the quantization parameter to the quantization unit 106 through the regulator 109.

On the other hand, the output of the quantization unit 105 is input to the VLC unit 106 and at the same time is input to the inverse quantization unit 110, inverse quantized, and then inverse discrete cosine transformed by the inverse DCT unit 111 to adder 112 Is entered.

The adder 112 adds the predictive image signal between the output of the inverse DCT unit 111 and the frame whose motion is compensated by the frame storage and prediction unit 113 to output the frame to the frame storage and prediction unit 113.

In addition, the frame storage and prediction unit 113 compensates the dynamic image when the video compression uses a continuous frame difference in order to remove the redundancy in time after delaying the output of the adder 112 by a predetermined frame time. Visually, using interframe compression techniques such as the Forward Prediction method, or an interpolation method that compensates for a dynamic image in a compressed video frame using the difference between a frame and a frame before or after it. Phosphorus error is eliminated and output to the subtractor 103 and the adder 112.

In this case, the picture start address coding unit 114 codes the picture start address and outputs a selection signal to the multiplexer 107 according to the value. The multiplexer 107 selects one of an output of the motion estimation unit 102 and an output of the VLC unit 106 according to the picture start address coding value and outputs the result to the transmission buffer 108.

In this case, the picture start address coding unit 114 encodes the picture start address in the extended area of the video bit stream or the area of the user data, and uses a relative position between two consecutive pictures.

The picture start address coding unit 114 has information about all picture types and their relative positions therebetween. However, only I pictures are required for high speed playback. So, to know the position of the next I picture, the positions of the P and B pictures between two I pictures must be summed.

Therefore, encoding information about the type and start address for all the pictures not only increases the bit stream size, but also consumes time during high-speed playback, thereby preventing a desired operation from being obtained.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problem, and a video bit stream encoding method capable of high-speed playback at a receiving end by configuring an MPEG I video bit stream by adding information about ISPA to a video GOP layer which is an object of the present invention. In providing.

A feature of the video bit stream encoding method according to the present invention for achieving the above object is that, if it is determined that the input picture is an I picture, calculating the IPSA by subtracting the start address of the current I picture from the start address of the previous I picture. And a step of storing a start address of the current picture, and a step of encoding the picture type and then encoding ISPA so that the multiplexer performs the above steps at the time of encoding the GOP layer and delivers them in a predetermined video bit stream.

Hereinafter, a preferred embodiment of a video bit stream encoding method according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram for performing a video bit stream encoding method according to the present invention.

In FIG. 2, the description of the configuration and operation of the same parts as those in FIG. 1 will be omitted, and the same blocks have the same reference numerals.

Referring to FIG. 2, the rest of the components except for the ISPA calculation and the encoder 115 are the same as those of FIG. 1, and thus descriptions thereof will be omitted. Only the operations of the IPSA calculation and the encoder 115 connected to the multiplexer 107 will be described in detail.

That is, the IPSA calculation and encoder 115 operates when the multiplexer 107 encodes the GOP layer, and encodes only the IPSA information in the definite data area and the user data area of the GOP layer.

The detailed operation of the IPSA calculation and encoder 115 will be described with reference to FIG.

That is, it is determined whether there are more pictures input (step 301). If it is determined that there are no more pictures, the next start code is called (step 302), and if it is determined that there are more pictures, it is determined whether or not it is an I picture (step 303).

If it is determined in step 303 that the picture is an I picture, the IPSA is calculated by subtracting the start address of the current I picture from the start address of the previous I picture (step 304).

The start address of the current picture is stored (step 305), the picture type is encoded (step 306), and the IPSA is encoded (step 307).

At this time, in order to encode the picture type, a code starting with 00 is allocated as follows.

0011: I picture, 0010: P picture, 0001: B picture

The encoding format is as follows.

Meanwhile, as another embodiment of the present invention, the value of the IPSA uses a relative position value between two I pictures, but may be coded as an absolute position value in the GOP layer for faster positioning when coding the position of each picture.

The code and coding format of the present invention can be used in any part of the group extension data area and the user data area.

As described above, according to the video bit stream encoding method according to the present invention, by encoding IPSA information in the video GOP layer, the decoder can know the start address of the I picture without any parsing of the entire video GOP layer. Since direct access to the next I picture is possible without any operation, there is an effect of reducing the bit stream size and enabling high-speed playback at the decoder.

Claims (3)

If it is determined that the input picture is an I picture, the step of calculating the I picture start address by subtracting the start address of the current I picture from the start address of the previous I picture, the step of storing the start address of the current picture, and encoding the picture type And a step of encoding the I picture start address, wherein the multiplexer performs the steps when encoding the GOP layer and delivers it in a predetermined video bit stream. The video bit stream encoding method of claim 1, wherein the I picture start address encoding step encodes only I picture start address information in an extended data area and a user data area of a GOP layer. The video bit stream encoding method of claim 1, wherein the I picture start address value can be encoded as an absolute position value in the GOP layer.