KR970001588Y1 - Sharpness voltage coacting noise reduction circuit using fet - Google Patents
Sharpness voltage coacting noise reduction circuit using fet Download PDFInfo
- Publication number
- KR970001588Y1 KR970001588Y1 KR92023786U KR920023786U KR970001588Y1 KR 970001588 Y1 KR970001588 Y1 KR 970001588Y1 KR 92023786 U KR92023786 U KR 92023786U KR 920023786 U KR920023786 U KR 920023786U KR 970001588 Y1 KR970001588 Y1 KR 970001588Y1
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- sharpness
- voltage
- fet
- effect transistor
- field effect
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Picture Signal Circuits (AREA)
Abstract
내용 없음.No content.
Description
제1도는 종래의 회로도.1 is a conventional circuit diagram.
제2도는 본 고안의 FET를 사용한 샤프니스전압 연동노이즈 감쇄회로도.2 is a sharpness voltage interlocking noise attenuation circuit using the FET of the present invention.
제3도(a)(b)(c)는 본 고안에 따른 주파수 파형도.Figure 3 (a) (b) (c) is a frequency waveform diagram according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
R1-R6 : 저항 C1-C2 : 콘덴서R1-R6: Resistor C1-C2: Capacitor
D1 : 다이오드 L : 코일D1: Diode L: Coil
FET : 전계효과 트랜지스터 10 : 마이크로 컴퓨터FET: field effect transistor 10: microcomputer
20 : 비디오 처리부 30 : CRT 증폭단20: video processor 30: CRT amplification stage
40 : 정류부40: rectifier
본 고안은 전계효과 트랜지스터(FET)를 사용한 샤프니스전압 연동노이즈 감쇄회로에 관한 것으로, 특히 약전계지역에서 노이즈에 의한 화질저하를 방지하기 위해 노이즈 대역주파수를 감쇄시켜 TV화면의 화질을 개선하는 것에 관한 것이다.The present invention relates to a sharpness voltage interlocked noise attenuation circuit using a field effect transistor (FET), and more particularly, to improve the picture quality of a TV screen by attenuating the noise band frequency to prevent image degradation caused by noise in a weak field region. will be.
일반적으로 텔레비젼 수상기의 화면상에는 일정한 크기와 농담을 구사하게 되는 최소단위의 화소들로 밀집 구성되어진바, 이들 각각의 화소에 평균밝기를 제공하는 영상신호를 제어하여 보다 선명한 화면을 얻을 수 있는 샤프니스회로가 제공된다.In general, the screen of a television receiver is densely composed of pixels of the smallest unit having a certain size and shade, and a sharpness circuit that can control a video signal providing average brightness to each pixel to obtain a clearer screen. Is provided.
종래에는 약전계지역에서 TV 영상신호 수신시 샤프니스 가변전압을 최저로 낮추더라도 2.5-3.5MHZ 노이즈대역주파수는 여전히 남아 화질저하 현상을 발생시키는 문제점이 있었다.Conventionally, even when the sharpness variable voltage is lowered to the minimum when receiving a TV video signal in a weak electric field, the 2.5-3.5MHZ noise band frequency still remains, causing a problem of deterioration in image quality.
따라서 본 고안은 상기의 지적한 문제점을 해결하기 위해서 전계효과 트랜지스터(FET)의 도통에 의한 코일(L)과 콘덴서(C) 및 저항(R3)을 수단으로 2.5-3.5MHZ 주파수 대역에 직렬트랩을 형성시켜 TV 화면의 노이즈를 감쇄시키는 회로를 제공하는데 그 목적이 있다.Therefore, the present invention forms a series trap in the 2.5-3.5MHZ frequency band by means of the coil L, the capacitor C and the resistor R3 by the conduction of the field effect transistor FET to solve the above-mentioned problems. The purpose is to provide a circuit for attenuating noise on a TV screen.
이후 첨부된 도면과 관련하여 상세히 설명하면 다음과 같다.Hereinafter, with reference to the accompanying drawings in detail as follows.
제1도는 종래의 샤프니스전압 연동노이즈 감쇄회로도로서, 샤프니스전압을 기조정하는 수단을 갖춘 마이크로 컴퓨터(10)로 부터 출력된 샤프니스전압을 상기 마이크로 컴퓨터(10)로 부터 최저로 가변시켜 비디오 처리부(20)의 샤프니스 제어단(C)에 입력한다.FIG. 1 is a conventional sharpness voltage interlocking noise attenuation circuit. The sharpness voltage output from the microcomputer 10 having a means for pre-adjusting the sharpness voltage is varied from the microcomputer 10 to the lowest, thereby processing the video processing unit 20. To the sharpness control stage (C).
또한 휘도(Y) 신호는 비디오 처리부(20)의 휘도신호입력단(IN)에 입력된 후 최저로 가변된 샤프니스전압과 함께 비디오 처리부(20)의 출력단(out)을 통해 CRT 증폭단(30)으로 출력된다.In addition, the luminance Y signal is input to the luminance signal input terminal IN of the video processor 20 and then output to the CRT amplifier 30 through the output terminal of the video processor 20 together with the sharpest voltage which is the lowest variable. do.
이때 제3도 (a)는 비디오 처리부(20)로 부터 최저로 가변된 샤프니스 전압연동노이즈파형도로서 2.5-3.5MHZ 주파수 대역에 노이즈가 그대로 존재함을 알 수 있다.In this case, FIG. 3A illustrates a sharpness voltage interlocking noise waveform which is the lowest from the video processor 20, and noise is present in the 2.5-3.5MHZ frequency band as it is.
제2도는 본 고안의 FET를 사용한 샤프니스전압 연동노이즈 감쇄회로도로서, 샤프니스전압을 기조정하는 수단을 갖춘 마이크로 컴퓨터(20)로 부터 출력된 샤프니스전압이 정류부(40)를 통해 정류된 다음 노드점(A)과 전압강하 저항(R1) 및 분배저항(R2)(R3)을 거쳐 비디오 처리부(20)의 샤프니스 제어단(C)에 입력하는 회로에 있어서,FIG. 2 is a sharpness voltage interlocked noise attenuation circuit using the FET of the present invention. In the circuit input to the sharpness control terminal (C) of the video processing unit 20 through the voltage drop resistor (R1) and distribution resistor (R2) (R3),
상기 노드점(A)은 분배저항(R4)(R5)을 통해 전계효과 트랜지스터(FET)의 게이트단에 인가되게 연결하고, 상기 전계효과 트랜지스터(FET)의 드레인단에 휘도 신호가 코일(L)과 콘덴서(C2)를 통해 인가되게 연결하고, 상기 전계효과 트랜지스터(FET)의 소오스단은 저항(R6)을 통해 접지연결하여 구성된다.The node point A is connected to the gate terminal of the field effect transistor FET through distribution resistors R4 and R5, and a luminance signal is applied to the drain terminal of the field effect transistor FET. And is connected to be applied through a capacitor (C2), the source terminal of the field effect transistor (FET) is configured by connecting to ground through a resistor (R6).
본 고안의 작용, 효과를 상세히 설명하면 다음과 같다.Referring to the operation, effects of the subject innovation in detail as follows.
제2도의 본 고안의 회로도에 있어서, 마이크로 컴퓨터(10)로 부터 출력된 샤프니스전압이 다이오드(D1)과 콘덴서(C1)로 구성된 정류부(40)를 통해 노드점(A)에 인가되는데 이때 샤프니스전압은 0.8-6.2V 가변 가능하다.In the circuit diagram of the present invention of FIG. 2, the sharpness voltage output from the microcomputer 10 is applied to the node point A through the rectifying section 40 composed of the diode D1 and the capacitor C1, wherein the sharpness voltage Is variable 0.8-6.2V.
따라서 가변되는 샤프니스전압이 분배저항(R4)(R5)에 의해 분압조정된 다음 전계효과 트랜지스터(FET) 게이트단에 인가된 전압이 1.5V 이상이면 전계효과 트랜지스터(FET)는 오프상태로 된다.Therefore, when the variable sharpness voltage is divided by the distribution resistors R4 and R5 and the voltage applied to the field effect transistor FET gate terminal is 1.5 V or more, the field effect transistor FET is turned off.
즉 제3도의 (b)도와 같은 샤프니스전압 연동노이즈파형도로서 2.5-3.5MHZ 주파수대역에 노이즈가 그대로 존재함을 알 수 있다.That is, as shown in (b) of FIG. 3, the sharpness voltage-linked noise waveform diagram shows that noise is still present in the 2.5-3.5MHZ frequency band.
이와 반대로 샤프니스전압이 분배저항(R4)(R5)에 의해 분압조정된 다음 전계효과 트랜지스터(FET) 게이트단에 인가된 전압이 1.5V 이하가 되면 전계효과 트랜지스터(FET)는 도통상태로 되기 시작한다.On the contrary, when the sharpness voltage is divided by the distribution resistors R4 and R5 and the voltage applied to the field effect transistor FET gate terminal becomes 1.5 V or less, the field effect transistor FET starts to be in a conductive state. .
따라서 휘도신호(Y)는 전계효과 트랜지스터(FET) 도통에 의해 상기 전계효과 트랜지스터(FET)의 드레인단에서 소오스단으로 흐르는바, 코일(L)과 콘덴서(C2) 및 저항(R6)에 의해서 휘도신호(Y)에 포함된 노이즈대역(2.5MHZ-3.5MHZ)의 주파수를 직렬트랩으로 형성시킨다.Therefore, the luminance signal Y flows from the drain terminal of the field effect transistor FET to the source terminal by the conduction of the field effect transistor FET, and the luminance is caused by the coil L, the capacitor C2, and the resistor R6. The frequency of the noise band (2.5MHZ-3.5MHZ) included in the signal Y is formed in a series trap.
즉 제3도의 (c)도와 같은 샤프니스전압 연동노이즈파형도로서, 2.5-3.5MHZ 주파수 대역에 노이즈가 감쇄된 상태로 나타나게 된다.That is, as the sharpness voltage interlocked noise waveform diagram as shown in FIG. 3 (c), noise is attenuated in the 2.5-3.5MHZ frequency band.
이와 같이 본 고안은 전계효과 트랜지스터(FET)를 사용하여 노이즈가 포함된 주파수대역을 감쇄시켜 직렬트랩을 형성시키므로써 부드러운 화질을 재현할 수 있는 효과가 있다.As such, the present invention has an effect of reproducing a smooth image quality by attenuating a frequency band containing noise using a field effect transistor (FET) to form a series trap.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92023786U KR970001588Y1 (en) | 1992-11-30 | 1992-11-30 | Sharpness voltage coacting noise reduction circuit using fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92023786U KR970001588Y1 (en) | 1992-11-30 | 1992-11-30 | Sharpness voltage coacting noise reduction circuit using fet |
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| Publication Number | Publication Date |
|---|---|
| KR940013946U KR940013946U (en) | 1994-06-29 |
| KR970001588Y1 true KR970001588Y1 (en) | 1997-03-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR92023786U KR970001588Y1 (en) | 1992-11-30 | 1992-11-30 | Sharpness voltage coacting noise reduction circuit using fet |
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| KR (1) | KR970001588Y1 (en) |
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1992
- 1992-11-30 KR KR92023786U patent/KR970001588Y1/en not_active IP Right Cessation
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| KR940013946U (en) | 1994-06-29 |
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