KR970000657B1 - Radio transmitter and receiver - Google Patents

Abstract

The wireless transmit-receive apparatus is comprised of detecting data collision not by the voltage level, but by the phase through a data collision detector(40); comparing data of a cable center party with data of a shield party; upon the data of the center party being less than that of the shield party, a comparing part(29) outputting a high signal; charging a capacitor(C1); maintaining the high signal state for a predetermined period of time, i.e. a discharging time upon the data of the center party being large, whereby making a reception enable signal(RX_EN) through a reception squelch circuit part(30) for the data collision detecting process being performed only if the data of the cable center party exists.

Description

Wireless Transceiver

1 is a block diagram of a wireless transmission and reception apparatus according to the prior art.

2 is an operation timing diagram of a receiver of a radio transceiver according to the prior art.

3 is an operation timing diagram of a data collision detection unit of a conventional radio transceiver.

4 is a block diagram of a wireless transmission and reception device according to the present invention.

5 is a block diagram of a data collision detection circuit of FIG.

6 is a timing diagram of the data collision detection circuit of FIG.

* Explanation of symbols for main parts of the drawings

20: cable 21: equalizer

23: receiver 24: data collision detection unit

25; First buffer 26: Second buffer

27,28,31: Transmission line 29: Comparison unit

30: receiving squelch circuit part 32: first line driving part

34: heartbeat generator 35: oscillator

36: timer signal 37: line drive enable part

38: second line driver 40: data collision detector

The present invention relates to a wireless transmission and reception apparatus, and more particularly, to a wireless transmission and reception apparatus capable of detecting a data collision by using a phase instead of a voltage level.

A transceiver for mounting a wireless transmitting and receiving device, that is, a transmitter and a receiver in a single device so as to communicate variously indoors or outdoors, conventionally, as shown in FIG. 1, has a data collision detection unit 100. A buffer (1) connected to the center of a cable (not shown), a buffer (2) connected to a shield of the cable, and an output from the two buffers (1, 2) are applied for low pass. Data collision is determined by comparing the outputs of the first and second filter parts 3 and 4 and the first and second filter parts 3 and 4 for extracting the average DC voltage level on the cable. A comparator 5 for transmitting the data, a heartbeat generator 6 for notifying that the transmission is finished after data transmission, an oscillator 7 for generating a 10MH _Z clock used as a collision signal, and Established by a line driver (8) for delivering a 10MH _Z clock signal to the control unit The receiver 200 is a high pass of the data input through the buffer (1) connected to the center of the cable to equalize (equalizer 9) to compensate for the low pass effect in the cable, and whether the signal is data It consists of a squelch circuit section 10 for discriminating noise and turning off the receiver at the packet end, and a differential line driver 11 for sending data to the control unit. If outlined as follows.

In the receiver 200, as shown in (a) of FIG. 2, the received data flowing in the center of the cable is passed through the first filter unit 3 and low-pass filtered to extract an average DC level value. b) As shown in FIG. 2, the received DC threshold voltage value, which is the average DC level shielded by the second filter unit 4 in the squelch circuit unit 10, is compared with the average DC level value of the first filter unit 3. As shown in (c), the differential line driver 11 is turned on to send data to the next stage.

In the data collision detection unit 100, as shown in FIG. 3 (a), a level shift (shielded average DC voltage level output from the comparison unit 5 through the second filter unit 4) is performed. The collision threshold voltage value, which is a level shifted value, is compared with the DC average voltage level output through the first filter unit 3, and when the average DC voltage level becomes negative, it is detected as a data collision and the line driver 8 is enabled. As shown in (b), the 10MH _Z clock is transferred to the next stage DTE (Date Terminal Equipment).

However, in the case of the conventional radio transceiver as described above, if a lot of load on the cable is generated, the voltage of the received data is attenuated and the voltage of the received data passing through the low pass filter is reduced, so that the input data due to the collision is negative than the collision threshold voltage. There is a problem in that data collision detection is not accurate because it does not recognize a collision, or normal data coming in through a cable is jumped by the noise of the cable and becomes negative than the collision threshold voltage, thus recognizing it as a data collision.

Accordingly, an object of the present invention is to provide a wireless transmission / reception apparatus capable of accurately detecting data collisions by detecting data collisions using phases instead of voltage levels in order to solve the above problems.

The wireless transmission and reception apparatus of the present invention for achieving the above object comprises a first buffer for inputting the center side data of the cable, a second buffer for inputting the shield side data of the cable, and the first and second buffers. A comparator for comparing the output to distinguish data and noise, a capacitor that is charged when the output of the first buffer is smaller than the output of the second buffer, a capacitor that discharges when the output of the first buffer is larger, and maintains a predetermined value; An equalizer for compensating for the low pass filtering effect of the cable on the received data, a reception squelch circuit unit for enabling or disabling the first line driver according to the predetermined value and the data compensated by the equalizer, and the reception squelch. A receiver configured to be enabled according to the output result of the tooth circuit section and including a first line driver for sending data to the next stage; An oscillator for generating a predetermined clock signal for use as a collision signal, a data collision detector for detecting a collision signal of data by inputting the output of the first buffer and the clock signal of the oscillator, and a fake after transmission A heartbeat generator for generating a collision signal, a line driver enable unit for enabling a second line driver by inputting the data collision detector, a heartbeat generator, and a timer signal applied from the outside, and the line And a data collision detection unit configured to be enabled according to the output of the driving enable unit and including a second line driver for transmitting the clock signal to the next stage.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

As shown in FIG. 4, the wireless transmitting / receiving apparatus of the present invention includes a receiver 23 and a data collision detector 24. The receiver is configured to receive shield-side data (RXI: Receiver Input) of the cable 20. A first buffer 25 for buffering as an input, a second buffer 26 for buffering with shielded data (CDS: Collision Detection Sense) of the cable 20, and the first and second buffers. The comparison unit 29 for comparing the outputs of the two buffers 25 and 26 to distinguish data and noise, and the data RXI value of the first buffer 25 are the data CDS of the second buffer 26. Value is less than the value of C, the capacitor C1 discharges to maintain a predetermined high value, and the low-pass filtering effect of the cable 20 is applied to the data RXI output from the first buffer 25. Equalizer 21 for compensating, a predetermined value held by the capacitor C1 and compensated by the equalizer 21 A receive squelch circuit unit 30 for enabling or disabling the first driver unit 32 according to the RXI EN and an enable signal RX EN, and enabled according to an output result of the receive squelch circuit unit. And a first line driver 32 for sending data to the next stage 22.

In addition, the data collision detection unit 24, the oscillator 35 for generating a clock signal of 10MH _Z for use as a collision signal, and when two or more data of different states are transmitted at the same time, that is, the first A data collision detector 40 for detecting a collision of data generated when the output of the first buffer 25 and the clock signal of the oscillator 35 are input at the same time, and a heartbeat enable signal (HBE) after data transfer is completed. A heartbeat generator 34 for generating a fake collision signal by inputting a transmission enable signal TX EN for transmitting a heartbeat enable, the data collision detector 40, a heartbeat generator 34, and A line drive enable part 37 composed of an AND gate to enable the second life driver 38 by inputting a timer signal Jabber 36 applied from the outside, and the line drive enable part 37 To the output of Therefore, the second line driver 38 is configured to be enabled and to transmit the clock signal to the next stage 39.

In addition, as illustrated in FIG. 5, the data collision detector 40 includes a capacitor C11 connected to an output terminal of the first buffer 25, and one side of the data collision detector 40 is connected to a power terminal to adjust a bias according to a resistance ratio. The other side is a resistor (R1) connected to the capacitor and a resistor (R2) grounded at one point (a) at one point (a), the gate is connected to the point (a) and the collector has a swing width of about 0V ~ 8.8V ( Connected to the power supply terminal through R3), the emitter is grounded and connected to the transistor Q1 turned on / off by the capacitor C11 and the collector of the transistor Q1 to apply a voltage applied to the resistor R3. When applied, the delay unit 41 delays for more than 10 n sec, and the output of the delay unit 41 and the output of the transistor Q1 are inputs. Configured to detect pulse edge values A first circuit 43 connected to an output terminal of the logic circuit unit 42 through a logic circuit unit 42, a resistor R connected between the output terminal of the logic circuit unit 42, and a power supply terminal, and a capacitor C12. And a latch 44 composed of two NAND gates connected to the output of the first inverter 43 and the output of the receiving squelch circuit 30 as their respective inputs, and connected to cross-input the respective outputs. It consists of a second inverter 45 connected to the output terminal of (44), the operation is as follows.

First, as shown in (a) of FIG. 6, when the low pass signal input from the center of the cable is input through the first buffer 25, the voltage of the resistor R3 in (b) is 0V to 8.8V. It has a swing width between and thus detects an edge value such as (c) through the logic circuit portion 42.

As soon as the edge becomes high, as shown in (d), the capacitor C12 is charged again when the edge is detected after maintaining the high for RC12 time constant (T = 100 n sec). The output goes low, and the low output resulting from the discharge whose edge is not detected subsequently goes high via the first inverter 43 as shown in (e), and the reception of (f) (G) is inputted to the latch 44 together with the output signal RX EN of the squelch circuit unit 30 until the output signal RX EN of the receiving squelch circuit unit 30 is disabled after a collision occurs. As indicated, it is a collision section.

That is, in the present invention, the first and second filter parts extracting the conventional average DC voltage are removed, and the data collision is detected through the data collision detector 40 at a phase other than the voltage level. Data of the cable center side and the shield side data are compared, and if the data value of the center side is small, the output of the comparator 29 is made high and charged to the capacitor C1, and then the data of the center side is large. In this case, by maintaining the high state for a predetermined time, that is, during the discharge time, the reception enable signal RX EN is generated through the reception squelch circuit 30 to perform data collision detection only when there is data on the cable center side.

As described above, according to the present invention, by detecting a data collision in phase, a more accurate detection is possible than in the case of using a voltage as in the prior art. By using digitalized logic instead of using it, the integration and reliability can be improved.

Claims (2)

A comparator for discriminating data and noise by comparing a first buffer for inputting the center-side data of the cable, a second buffer for inputting the shield-side data of the cable, and an output of the first and second buffers And a capacitor for charging when the output of the first buffer is smaller than the output of the second buffer, and discharging to maintain a predetermined value when the output of the first buffer is large. Compensating the low pass filtering effect of the cable on data output from the first buffer. An equalizer for receiving, a receiving squelch circuit unit for enabling or disabling the first line driver according to the predetermined value and the data compensated by the equalizer, and an enable signal according to the output result of the receiving squelch circuit unit for data to the next stage. A receiver configured to include a first line driver for sending; An oscillator for generating a predetermined clock signal for use as a collision signal, a data collision detector for detecting a data collision signal by inputting the output of the first buffer and the clock signal of the oscillator, and a fake collision signal after signal transmission A heartbeat generator for generating a signal, a line driver enabler for enabling a second line driver by inputting the data collision detector, a heartbeat generator, and a timer signal applied from the outside, and the line driver in And a data collision detection unit configured to be enabled according to the output of the enable unit and including a second line driver for transmitting the clock signal to the next stage. The resistor of claim 1, wherein the data collision detector has a capacitor C11 connected to an output terminal of the first buffer, one side of which is connected to a power terminal, and the other side of which a ground is connected to the capacitor C11 and one side thereof. A resistor R1 connected to R2, a gate connected to the point a, a collector connected to a power supply terminal through a resistor R3, an emitter connected to a grounded transistor, a delay connected to a collector of the transistor, A logic circuit portion for outputting a high signal when only one of the inputs is high by inputting an output of the delayer and an output of a transistor; a resistor R connected between an output terminal of the logic circuit portion and a power supply terminal; A first inverter connected to an output terminal of the logic circuit unit through C12), a latch for inputting an output of the first inverter and an output of the receiving squelch circuit unit, and a second connected to an output terminal of the latch; Mobile transceiver, characterized in that consisting of butter.