KR960704270A - LOW POWER, HIGH PERFORMANCE, ON-CHIP CACHE WITH NO STALL AFTER A WRITE HIT - Google Patents

Abstract

An n-type set associative cache is provided for storing address and information (e.g., data, instructions) blocks in a plurality of respective but independently accessible address and information memory arrays or banks. The address and information arrays are accessible during different stages of the two stage CPU block. The information array is only accessed if a hit has occurred in the associated address array. This configuration reduces one cycle processing power and power consumption.

Description

LOW POWER, HIGH PERFORMANCE, ON-CHIP CACHE WITH NO STALL AFTER A WRITE HIT

As this is a public information case, the full text was not included.

3 is a schematic block diagram of a cache arranged in accordance with the present invention,

4 is a flow chart for operating the cache of FIG. 3 in accordance with the present invention;

5 is a timing diagram illustrating an access step of a data cache according to the present invention.

Claims (31)

In an n (n is an integer) type associative cache that stores information accessible by a request address, an n information array in which an information block is accessible according to an allocation address, and an n address in which an address is independently stored in the n information array. And an array of n addresses, wherein addresses stored in said n arrays are assigned to information blocks of said n information arrays, respectively. 2. The n-type set associative cache of claim 1, further comprising a decoder having a portion of the yog address and having an output coupled to the n-address array. 3. The n-type set associative cache of claim 2, further comprising another decoder having a portion of the request address and having an output coupled to the n-information array. 4. The associative set associative cache of claim 3, further comprising a clock circuit coupled to said decoders. 5. The n-type set associative cache of claim 4, wherein the clock circuit operates the decoders to operate at different times. 6. The n-type set associative cache of claim 5, wherein the clock circuit provides a two stage CPU cycle, and wherein the different times are each related to the two stages. The apparatus of claim 1, further comprising a comparator for each of the n address arrays for receiving (a) a portion of a request address and (b) an address accessed to such an address array based on the request address. n-type set associative cache. 2. The apparatus of claim 1, further comprising drivers having outputs respectively coupled to information blocks stored in the n information arrays, wherein the drivers having outputs coupled to one information block of the n information arrays comprise: information of the one information array; And an n-type set associative cache, coupled to receive the output of the comparator of an address array that stores the address assigned to the block. The n-type set associative cache according to claim 1, further comprising a clock circuit for activating access to said n information array and said n address array at different times connected to said n information array and said n address array. . An n (n is an integer) type associative cache for storing information accessible by a request address, the n-address array for storing a plurality of addresses, and a plurality of blocks of information accessible according to the allocated addresses, respectively. An n information array, wherein the n information arrays are associated with the n address arrays by being associated with n addresses, and the n information arrays are one address each assigned to a plurality of information blocks of the associated information array. N comparators each having a plurality of addresses of an array, the n address array and the n information array, the n comparators for respectively outputting the output of the n address array, wherein one input of each of the n comparators is connected to an output of the address array The other input of the big bits is n for receiving a signal corresponding to the request address. Intersects, drivers for each of the n information arrays, wherein the drivers have outputs coupled to the plurality of information blocks, respectively, each of the drivers (a) a signal corresponding to the request address and (b) such information. And n drivers for receiving as inputs a signal corresponding to an output from one of said n comparators receiving an output from an address array associated with the array. 11. The n-type set associative cache of claim 10, further comprising a decoder having a portion of the request address and having an output coupled to the n-address array. 12. The n-type set associative cache of claim 11, further comprising another decoder having a portion of the request address and having an output coupled to the n information array. 13. The n-type set associative cache of claim 12, further comprising a clock circuit coupled to the decoders, wherein the clock circuit operates the decoders to operate at different times. 12. The n-type aggregate associative cache of claim 10, connected to the n information array and the n address array to activate access to the n information array and the n address array at different times. In an n (n is an integer) type associative cache for storing information accessible by a request address, an n address array for storing a plurality of addresses, and a plurality of blocks of information accessible according to the allocated addresses, respectively. An n information array, wherein the n information array is associated with each of the n address arrays by being associated with n addresses, and the n information arrays are one address, each address being allocated for a plurality of information blocks of the related information array. N address arrays and n information arrays having a plurality of addresses of the array, means for verifying whether a request address matches a special address stored in a selected storage location in each of said n address arrays, wherein the special address is in one of the n address arrays If verified, store the verified address Is n way set associative cache comprising: means for accessing only the special information are associated with which of the n array address array. 16. The n-type set associative cache of claim 15, wherein the access means accesses only the information blocks of the special information array assigned to the verified address. 16. The n-type set associative cache of claim 15, wherein said verifying means simultaneously verifies all of said n address arrays for matching with said request address. 16. The n-type set associative cache according to claim 15, wherein said verification means and said access means are operated at different times. 19. The n-type aggregate associative cache of claim 18, wherein said different times correspond to steps in a CPU cycle. 16. The n-type associative cache of claim 15, wherein said verifying means comprises decoder means coupled to receive a first portion of a request address and to generate said selected storage location therefrom. 21. The n-type set associative cache of claim 20, comprising a comparator for each of the n address arrays for receiving a second portion of a yog address and an access address stored in the selected storage location. 22. The n-type set associative cache of claim 21, wherein said access means for each array of information is responsive to the output of said comparator of an address array associated with said array of information. A clock providing a plurality of steps in a CPU cycle, a memory in which a plurality of addresses and a plurality of allocated information blocks are stored, and during one of the steps in response to a request address, which of the plurality of stored addresses is associated with the request address. Means for verifying whether or not there is matching, and means for accessing the one assigned to the verified address of the plurality of information blocks during the other steps of the step, whereby one cycle throughput is achieved. Method set association memory. 24. The n-type aggregate associative cache of claim 23, wherein said access means performs a read operation in said other step after a read hit in said one step. 24. The n-type associative cache of claim 23, wherein said access means performs a write operation in said other step after a write hit in said one step. 27. The n-type associative cache of claim 25, wherein said access means performs a read in one CPU cycle after a write hit in the immediately preceding CPU cycle. 24. The n-type aggregate associative cache of claim 23, wherein said CPU cycle has two stages. Memory for storing a plurality of addresses and a plurality of allocated information blocks, respectively, and means for verifying, during one time period, which of the plurality of stored addresses matches the request address in response to a request address. And an means for accessing the one assigned to the verified address of the plurality of information blocks during different time periods, whereby power consumption reduction is achieved. 29. The n-type associative cache of claim 28, wherein said access means performs a read in said another time period after a read hit in said one time period. 29. The n-type set associative cache of claim 28, wherein said access means performs a write in said another time period after a write hit in said one time period. 29. The n-type set associative cache of claim 28, wherein the time periods are steps of one CPU cycle. ※ Note: The disclosure is based on the initial application.