KR960040049A - High Level Processor Block (MPH) Integration Method in Electronic Switching System - Google Patents

High Level Processor Block (MPH) Integration Method in Electronic Switching System Download PDF

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Publication number
KR960040049A
KR960040049A KR1019950007762A KR19950007762A KR960040049A KR 960040049 A KR960040049 A KR 960040049A KR 1019950007762 A KR1019950007762 A KR 1019950007762A KR 19950007762 A KR19950007762 A KR 19950007762A KR 960040049 A KR960040049 A KR 960040049A
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KR
South Korea
Prior art keywords
board
high level
level processor
mph
processor block
Prior art date
Application number
KR1019950007762A
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Korean (ko)
Other versions
KR0145540B1 (en
Inventor
김진기
최이덕
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950007762A priority Critical patent/KR0145540B1/en
Publication of KR960040049A publication Critical patent/KR960040049A/en
Application granted granted Critical
Publication of KR0145540B1 publication Critical patent/KR0145540B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Hardware Redundancy (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

본 발명은 상위 제어를 담당하는 상위 레벨 프로세서 블럭 내의 상위 프로세서 ＆ 메모리 관리보드 64S (MPMA64S)와 이중화 제어채널보드 (DCCA)를 하나의 보드로 통합하여 시스템 규모를 축소시키는 전전자 교환기 내 상위 레벨 프로세서 블럭 (MPH)집적화 방법에 관한 것으로, 일반적인 전전자 교환기 내 상위 프로세서 백-보드는 교환기 시스템의 규모에 비해 상대적으로 크게 구성되어 있어, 설계 면적을 많이 차지하는 불편함 및 상호 데이타 통로 길이가 길어져 데이타 유실 등의 문제가 있는 바, 본 발명은 이런 문제점을 해결코자, 기존에 두개의 보드에서 행해지던 기능을 하나의 보드에 집적시켜 그와 동일한 기능을 하도록 하므로써, 경제적 잇점이 있을 뿐만아니라, 상호 데이타 통로 역시 축소되므로 데이타 유실 등의 문제가 제거되어 시스템의 신뢰성을 향상시키는 효과가 있다.The present invention integrates the upper processor & memory management board 64S (MPMA64S) and the redundant control channel board (DCCA) in the upper level processor block in charge of the upper level control into a single board. Block (MPH) aggregation method, the upper processor back-board in the general electronic switchboard is relatively large compared to the size of the switchboard system, the inconvenience of occupying a large design area and the length of the mutual data path length, data loss In order to solve this problem, the present invention integrates the functions previously performed on two boards into one board to perform the same function, thereby providing economic benefits and mutual data path. It also shrinks, eliminating problems such as data loss and trusting the system. The effect of improving.

Description

전전자 교환기 내 상위 레벨 프로세서 블럭 (MPH) 집적화 방법High Level Processor Block (MPH) Integration Method in Electronic Switching System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 의해 집적화된 상위 프로세서 백-보드 (MPBB) 실장도, 제 4도는 본 발명에 의한 상위 프로세서 ＆ 이중화 제어 보드 (MPDA) 블럭도이다.FIG. 3 is an upper processor back-board (MPBB) mounting diagram integrated by the present invention, and FIG. 4 is an upper processor & redundant control board (MPDA) block diagram according to the present invention.

Claims (1)

전전자 교환기 내 상위 레벨 프로세서 블럭 (MPH)집적화 방법에 있어서, 상위 프로세서 및 메모리 관리 기능이 있는 상위 프로세서 ＆ 메모리 관리보드 64S (MPMA64S) (12)와, 상위 프로세서 블럭의 이중화 구성을 제어하는 이중화 제어채널 보드 (DCCA) (14) 2개 보드의 기능을 집적시켜 하나의 상위 프로세서 ＆ 이중화 제어보드 (MPDA) (15)를 만들고, 이를 실장하는 각 백-보드들을 집적화시켜 전전자 교환기 내 전체 설계면적을 축소시키는 것을 특징으로 하는 전전자 교환기 내 상위 레벨 프로세서 블럭 (MPH)집적화 방법.A high level processor block (MPH) integration method in an electronic switching system, comprising: a high level processor and a memory management board 64S (MPMA64S) 12 having a high level processor and a memory management function, and a redundancy control for controlling a redundant configuration of the high level processor block Channel Board (DCCA) (14) Integrates the functionality of two boards to form a single High Processor & Redundant Control Board (MPDA) (15), and integrates each back-board that mounts it to the overall design area in the electronic switchboard. And a method for integrating a high level processor block (MPH) in an all-electronic exchange. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950007762A 1995-04-03 1995-04-03 Method of integrating the upper level processor block in ess KR0145540B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950007762A KR0145540B1 (en) 1995-04-03 1995-04-03 Method of integrating the upper level processor block in ess

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950007762A KR0145540B1 (en) 1995-04-03 1995-04-03 Method of integrating the upper level processor block in ess

Publications (2)

Publication Number Publication Date
KR960040049A true KR960040049A (en) 1996-11-25
KR0145540B1 KR0145540B1 (en) 1998-08-17

Family

ID=19411472

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950007762A KR0145540B1 (en) 1995-04-03 1995-04-03 Method of integrating the upper level processor block in ess

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KR (1) KR0145540B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100810860B1 (en) * 2001-12-28 2008-03-06 엘지노텔 주식회사 Router and exchange concolidated board and method of operating in IP-PBX

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100810860B1 (en) * 2001-12-28 2008-03-06 엘지노텔 주식회사 Router and exchange concolidated board and method of operating in IP-PBX

Also Published As

Publication number Publication date
KR0145540B1 (en) 1998-08-17

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