KR960039975A

KR960039975A - Image Delay Compensation Circuit of Closed Circuit Television System

Info

Publication number: KR960039975A
Application number: KR1019950010179A
Authority: KR
Inventors: 임영재
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-04-27
Filing date: 1995-04-27
Publication date: 1996-11-25

Abstract

1. 청구범위에 기재된 발명이 속하는 기술분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 폐쇄회로 텔레비젼시스템의 영상제어부의 영상지연보상회로에 관한 것이다.The present invention relates to an image delay compensation circuit of an image control unit of a closed circuit television system.

2. 발명이 해결하고자하는 기술적 과제2. The technical problem to be solved by the invention

본 발명의 목적은 폐쇄회로 텔레비젼시스템의 카메라부와 영상제어부간의 통신케이블의 길이변화에 따른 영상신호의 시간지연을 보상하는 영상지연보상회로를 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide an image delay compensation circuit for compensating time delay of an image signal according to a change in the length of a communication cable between a camera portion and an image control portion of a closed circuit television system.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

본 발명은 폐쇄회로 텔레비젼시스템의 영상제어부에 있어서, 소정 제1동기신호, 제1브랭킹펄스신호, 제1버스트 프래그 펄스신호, 제1서브캐리어신호를 생성출력하는 제1동기신호생성수단과, 상기 제1동기신호 생성수단으로부터 입력되는 VDD신호와 HDD신호를 소정시간 지연하여 출력하는 지연수단과, 상기 지연수단으로부터 출력되는 VDD신호 및 HDD신호를 수평리셋 및 수직리셋단자로 입력받아 이에 응답하여 상기 제1동기신호생성수단의 출력신호보다 상기 소정시간만큼 지연된 제2동기신호, 제2버스트 프래그 펄스신호, 제2서브캐리어신호를 생성출력하는 제2동기신호생성수단과, 일측입력단으로 상기 제1버스트 프래그 펄스신호와 제1서브캐리어신호를 입력받으며, 이측입력단으로 제2서브캐리어신호와 제2버스트프래그펄스신호를 입력받고, 소정 선택 신호에 대응하여 양측입력단 중 어느 하나의 입력단신호들을 선택적 출력하는 제1스위칭수단과, 상기 제1동기신호와 제2동기신호를 각각 입력받아 상기 선택신호에 응답하여 하나의 입력 동기신호를 선택적 출력하는 제2스위칭수단과, 상기 제2스위칭수단으로부터 출력되는 동기신호와, 상기 제1스위칭수단으로부터 버스트신호를 입력받으며, 상기 두 입력신호를 혼합하여 버스트동기신호를 생성출력하는 신호결합수단으로 구성한다.According to an aspect of the present invention, there is provided an image control unit of a closed circuit television system, comprising: first synchronizing signal generating means for generating and outputting a predetermined first synchronizing signal, a first blanking pulse signal, a first burst flag pulse signal, and a first subcarrier signal; A delay means for delaying and outputting the VDD signal and the HDD signal inputted from the first synchronous signal generating means for a predetermined time; and receiving the VDD signal and the HDD signal output from the delay means through the horizontal reset and vertical reset terminals. Second synchronization signal generation means for generating and outputting a second synchronization signal, a second burst flag pulse signal, and a second subcarrier signal delayed by the predetermined time from the output signal of the first synchronization signal generation means, and to one side input terminal. The first burst flag pulse signal and the first subcarrier signal are input, and the second subcarrier signal and the second burst flag pulse signal are input to the two-sided input terminal. A first switching means for selectively outputting any one of input signals of both input terminals in response to the tack signal, and receiving the first synchronous signal and the second synchronous signal, respectively, and selectively selecting one input synchronous signal in response to the selection signal; A second combining means for outputting, a synchronizing signal output from the second switching means, a burst signal from the first switching means, and a signal combining means for generating and outputting a burst synchronization signal by mixing the two input signals. Configure.

4. 발명의 중요한 용도.4. Important uses of the invention.

본 발명은 폐쇄회로 텔레비전시스템에서 중요히 사용될 수 있다.The present invention can be importantly used in a closed circuit television system.

Description

Image Delay Compensation Circuit of Closed Circuit Television System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 바람직한 일 실시예에 따른 영상지연보상회로의 블럭구성도이다.2 is a block diagram of an image delay compensation circuit according to an exemplary embodiment of the present invention.

Claims

An image control unit of a closed circuit television system; First synchronous signal generating means for generating and outputting a predetermined first synchronous signal, a first blanking pulse signal, a first burst flag pulse signal, and a first subcarrier signal; Delay means for delaying the VDD signal and the HDD signal input from the first synchronous signal generation means for a predetermined time and outputting the delayed signal; The second synchronous signal and the second burst flag which are delayed by the predetermined time from the output signal of the first synchronous signal generation means in response to the VDD signal and the HDD signal output from the delay means are input to the horizontal reset and vertical reset terminals. Second synchronous signal generation means for generating and outputting a pulse signal and a second subcarrier signal; The first burst flag signal and the first subcarrier signal are input to one input terminal, and the second subcarrier signal and the second burst flag pulse signal are input to the second input terminal, and the two input terminals are input in response to a predetermined selection signal. First switching means for selectively outputting any one input terminal signal; Second switching means for receiving the first synchronization signal and the second synchronization signal, respectively, and selectively outputting one input synchronization signal in response to the selection signal; And a signal combining means for receiving a synchronization signal output from the second switching means and a burst signal from the first switching means, and combining the two input signals to generate and output a burst synchronization signal. Compensation circuit.

The image delay compensation circuit of claim 1, wherein the switching means is a multiplexer.

An image delay compensation circuit according to claim 1, wherein said delay means is a monostable multivibrator.

3. An image delay compensation circuit according to claim 2, wherein said delay means is a monostable multivibrator.

※ Note: The disclosure is based on the initial application.