KR960039168A - Method and apparatus for setting polishing endpoints in semiconductor manufacturing - Google Patents

Method and apparatus for setting polishing endpoints in semiconductor manufacturing Download PDF

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Publication number
KR960039168A
KR960039168A KR1019950008053A KR19950008053A KR960039168A KR 960039168 A KR960039168 A KR 960039168A KR 1019950008053 A KR1019950008053 A KR 1019950008053A KR 19950008053 A KR19950008053 A KR 19950008053A KR 960039168 A KR960039168 A KR 960039168A
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South Korea
Prior art keywords
polishing
interlayer film
electrical signal
setting
end point
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KR1019950008053A
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Korean (ko)
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KR0166848B1 (en
Inventor
전영권
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문정환
엘지반도체 주식회사
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Priority to KR1019950008053A priority Critical patent/KR0166848B1/en
Publication of KR960039168A publication Critical patent/KR960039168A/en
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Publication of KR0166848B1 publication Critical patent/KR0166848B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/005—Control means for lapping machines or devices
    • B24B37/013—Devices or means for detecting lapping completion

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

본 발명은 반도체 제조시의 연마종점 설정방법 및 장치에 관한 것으로, 반도체 장치의 층간막의 평탄화공정으로서 연마공정을 적용할 때 층간막 하지층의 영향받는 일없이 그 연마종정을 설정할 수 있도록 한 것이다. 본 발명은 기판상의 임의의 층간막을 연마하는 공정의 연마종점을 설정하는 방법에 있어서, 상기 층간막의 표면에 입사광을 조사하는 단계와, 상기 입사광의 반사광을 검출하여 전기적 신호로 변환시키는 단계, 및 상기전기적 신호의 변화량이 임의의 오차범위내에 들어가는 시점을 연마종점으로 설정하는 단계를 포함하여 이루어지는 반도체 제조시의 연마공정에 있어서의 연마종점 설정방법을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for setting a polishing end point in semiconductor manufacturing, wherein the polishing seed can be set without being affected by the underlying layer of the interlayer film when the polishing step is applied as a planarization step of the interlayer film of the semiconductor device. The present invention provides a method for setting a polishing end point for polishing an arbitrary interlayer film on a substrate, comprising: irradiating incident light to a surface of the interlayer film, detecting reflected light of the incident light and converting the reflected light into an electrical signal, and A polishing end point setting method in a polishing step in manufacturing a semiconductor comprising a step of setting a point of time at which an electric signal change amount falls within an arbitrary error range as a polishing end point.

Description

반도체 제조시의 연마종점 설정방법 및 장치Method and apparatus for setting polishing endpoints in semiconductor manufacturing

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 연마종점 검출장치의 개략도.1 is a schematic view of the polishing endpoint detecting apparatus of the present invention.

Claims (8)

기판상에 형성된 층간막을 연마하는 공정의 연마종점을 결정하는 방법에 있어서, 연마대상인 상기 층간막의 표면정보를 검출하고 분석하여 연마종점을 설정하는 것을 특징으로 하는 반도체 제조시의 연마종점 설정방법.A method for determining the polishing endpoint of a step of polishing an interlayer film formed on a substrate, wherein the polishing endpoint is set by detecting and analyzing surface information of the interlayer film to be polished and setting the polishing endpoint. 제1항에 있어서, 상기 층간막의 표면정보는 표면 토폴로지의 관련정보인 것을 특징으로 하는 반도체 제조시의 연마종점 설정방법.The method of claim 1, wherein the surface information of the interlayer film is related information of a surface topology. 제1항에 있어서, 상기 연마종점을 결정하는 방법이 상기 층간막의 표면에 입사광을 조사하는 단계와, 상기 입사광의 반사광을 검출하여 전기적 신호로 변환시키는 단계, 및 상기 전기적 신호의 변화량이 임의의 오차범위내에 들어가는 시점을 연마종점으로 설정하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 제조시의 연마종정 설정방법.The method of claim 1, wherein the method of determining the polishing end point comprises irradiating incident light to a surface of the interlayer film, detecting the reflected light of the incident light, converting the reflected light into an electrical signal, and an amount of change in the electrical signal. A polishing seed setting method in manufacturing a semiconductor, comprising the step of setting the starting point within the range as the polishing end point. 제3항에 있어서, 상기 층간막을 절연막이나 전도성막 또는 이들이 혼합되어 구성된 막을 포함하는 것을 특징으로 하는 반도체 제조시의 연마종점 설정방법.The method of claim 3, wherein the interlayer film comprises an insulating film, a conductive film or a film formed by mixing them. 제3항에 있어서, 상기 입사광은 그 파장범위가 1550 이상인 것을 특징으로 하는 반도체 제조시의 연마종점 설정방법.4. The method as set forth in claim 3, wherein the incident light has a wavelength range of 1550 or more. 제3항에 있어서, 상기 입사광의 입사강의 45˚∼85˚ 범위인 것을 특징으로 하는 반도체 제조시의 연마종점 설정방법.4. The polishing endpoint setting method of claim 3, wherein the incident light is in the range of 45 ° to 85 ° of the incident steel. 제3항에 있어서, 상기 전기적 신호는 전압신호인 것을 특징으로 하는 반도체 제조시의 연마종점 설정방법.4. The method of claim 3, wherein the electrical signal is a voltage signal. 기판상의 임의의 층간막을 연마하는 공정의 연마종점을 결정하기 위한 장치에 있어서, 상기 층간막의 표면으로부터의 반사광을 수집하여 전기적 신호로 변환시키는 수광소자와, 상기 전기적 신호를 증폭시키는 증폭기, 상기 증폭된 전기적 신호를 필터링하는 필터, 상기 전기적 신호를 클리핑하는 리미터, 상기 전기적 신호를 삼각파로 재구성하는 적분기, 상기 적분기로부터 출력된 신호를 반전시키는 인버터 딜레이단, 상기 인버터 딜레이단을 거친 신호와 상기 적분기로부터 출력되어 상기 인버터 딜레이단을 거치지 않은 신호를 비교하여 상기삼각파의 진폭이 일정한 오차범위내에서 전후 증감이 더 이상 일어나지 않을 때를 연마종점으로 설정하는 비교기, 및 상기 비교리로부터의 출력을 피드백시키는 파라미터 콘트롤러를 포함하여 구성된 것을 특징으로 하는 반도체 제조시의 연마종점 설정장치.An apparatus for determining the polishing endpoint of a process of polishing an arbitrary interlayer film on a substrate, the apparatus comprising: a light receiving element for collecting reflected light from the surface of the interlayer film and converting the light into an electrical signal; an amplifier for amplifying the electrical signal; A filter for filtering an electrical signal, a limiter for clipping the electrical signal, an integrator for reconstructing the electrical signal into a triangular wave, an inverter delay stage for inverting a signal output from the integrator, a signal passing through the inverter delay stage and an output from the integrator And a comparator for comparing the signals that have not passed through the inverter delay stage to set the polishing end point when the amplitude of the triangular wave is no longer increased or decreased within a constant error range, and a parameter controller for feeding back the output from the comparison unit. That configured including A polishing end point setting device for manufacturing a semiconductor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950008053A 1995-04-07 1995-04-07 End point detecting apparatus and method of semiconductor process KR0166848B1 (en)

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KR1019950008053A KR0166848B1 (en) 1995-04-07 1995-04-07 End point detecting apparatus and method of semiconductor process

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KR960039168A true KR960039168A (en) 1996-11-21
KR0166848B1 KR0166848B1 (en) 1999-02-01

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100543195B1 (en) * 1998-12-30 2006-04-06 주식회사 하이닉스반도체 Chemical mechanical polishing equipment
KR100581177B1 (en) * 1997-08-19 2006-05-22 마이크론 테크놀로지 인코포레이티드 Method and apparatus for detecting the endpoint in chemical-mechanical polishing of semiconductor wafers

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6511363B2 (en) * 2000-12-27 2003-01-28 Tokyo Seimitsu Co., Ltd. Polishing end point detecting device for wafer polishing apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100581177B1 (en) * 1997-08-19 2006-05-22 마이크론 테크놀로지 인코포레이티드 Method and apparatus for detecting the endpoint in chemical-mechanical polishing of semiconductor wafers
KR100543195B1 (en) * 1998-12-30 2006-04-06 주식회사 하이닉스반도체 Chemical mechanical polishing equipment

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