KR960039153A - Wiring layer with antifuse of semiconductor device and forming method - Google Patents

Wiring layer with antifuse of semiconductor device and forming method Download PDF

Info

Publication number
KR960039153A
KR960039153A KR1019950009608A KR19950009608A KR960039153A KR 960039153 A KR960039153 A KR 960039153A KR 1019950009608 A KR1019950009608 A KR 1019950009608A KR 19950009608 A KR19950009608 A KR 19950009608A KR 960039153 A KR960039153 A KR 960039153A
Authority
KR
South Korea
Prior art keywords
wiring layer
forming
film
semiconductor device
antifuse
Prior art date
Application number
KR1019950009608A
Other languages
Korean (ko)
Other versions
KR0151654B1 (en
Inventor
오한수
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950009608A priority Critical patent/KR0151654B1/en
Publication of KR960039153A publication Critical patent/KR960039153A/en
Application granted granted Critical
Publication of KR0151654B1 publication Critical patent/KR0151654B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive

Abstract

본 발명에 의한 반도체 장치의 앤티퓨즈를 가진 배선층과 그 형성방법에서 앤티퓨즈를 가진 배선층의 형성 방법으로는 반도체소자의 표면보호막상에 제1배선층을 형성시키는 단계와, 제1배선층의 사이를 매립시키면서, 제1배선층을 덮는 절연물질막을 형성시키는 단계와, 절연물질막을 에치백하여 제1배선층의 상면을 노출시키는 단계와, 절연물질막과 제1배선층의 상면에 유전물질막을 형성시키는 단계와, 유전물질막의 상면에 도전물질층을 형성시키고, 앤티퓨즈형성부위를 패터닝하여 제1배선층과 직교하면서, 유전물질막에 의해 제1배선층의 상면과 교차되는 부위가 절연되는 제2배선층을 형성시키는 단계를 포함하여 이루어지며, 앤티퓨즈를 가진 배선층은 반도체소자의 배선층인 제1배선층과, 제1배선층 위에서 앤티퓨즈형성부위에 형성시킨 유전체막과, 유전체막 위에 제1배선층과 직교하면서, 유전물질막에 의해 제1배선층의 상면과 교차되는 부위가 절연되도록 형성시킨 제2배선층으로 이루어지고, 제1배선층과 제2배선층의 사이에 유전체막이 평면적으로 형성되는 것을 특징으로 한다.In the semiconductor device according to the present invention, a wiring layer having an antifuse and a method of forming the wiring layer having an antifuse in the method of forming the same include forming a first wiring layer on a surface protective film of a semiconductor device, and filling the gap between the first wiring layer. Forming an insulating material film covering the first wiring layer, etching back the insulating material film to expose the top surface of the first wiring layer, and forming a dielectric material film on the top surface of the insulating material film and the first wiring layer; Forming a conductive material layer on the upper surface of the dielectric material film, patterning the anti-fuse forming region orthogonal to the first wiring layer, and forming a second wiring layer insulated from the upper surface of the first wiring layer by the dielectric material film. And an antifuse wiring layer formed on the antifuse forming portion on the first wiring layer, which is a wiring layer of a semiconductor device, and the first wiring layer. And a second wiring layer formed so as to insulate a portion intersecting the upper surface of the first wiring layer by the dielectric material film while being orthogonal to the first wiring layer on the whole film and between the first wiring layer and the second wiring layer. The dielectric film is formed in a planar manner.

Description

반도체 장치의 앤티퓨즈를 가진 배선층과 그 형성방법Wiring layer with antifuse of semiconductor device and forming method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 반도체 장치의 앤티퓨즈를 가진 배선층의 형성단계를 도시한 도면, 제3도는 본 발명에 의한 반도체 장치의 앤티퓨즈를 가진 배선층의 구조를 설명하기 위한 도면.2 is a view showing a step of forming a wiring layer having an antifuse of a semiconductor device according to the present invention, and FIG. 3 is a view for explaining the structure of a wiring layer having an antifuse of a semiconductor device according to the present invention.

Claims (7)

반도체 장치의 앤티퓨즈를 가진 배선층 형성방법에 있어서, 1) 반도체소자의 표면보호막상에 제1배선층을 형성시키는 단계와, 2) 상기 제1배선층의 사이를 매립시키면서, 상기 제1배선층을 덮는 절연물질막을 형성시키는 단계와, 3) 상기 절연물질막을 에치백하여 상기 제1배선층의 상면을 노출시키는 단계와, 4) 상기 절연물질막과 상기 제1배선층의 상면에 유전물질막을 형성시키는 단계와, 5) 상기 유전물질막의 상면에 도전물질층을 형성시키고, 앤티퓨즈형성부위를 패턴닝하여 상기 제1배선층과 직교하면서, 상기 유전물질막에 의해 상기 제1배선층의 상면과 교차되는 부위가 절연되는 제2배선층을 형성시키는 단계를 포함하여 이루어진 반도체 장치의 앤티퓨즈 형성방법.A method of forming a wiring layer having an antifuse of a semiconductor device, comprising: 1) forming a first wiring layer on a surface protective film of a semiconductor device; and 2) insulating covering the first wiring layer while filling the first wiring layer. Forming a material film, 3) etching back the insulating material film to expose a top surface of the first wiring layer, and 4) forming a dielectric material film on the top surface of the insulating material film and the first wiring layer; 5) forming a conductive material layer on the top surface of the dielectric material film, patterning an anti-fuse forming region, and orthogonal to the first wiring layer, and insulating a portion crossing the top surface of the first wiring layer by the dielectric material film. And forming a second wiring layer. 제1항에 있어서, 상기 1) 단계에서 상기 제1배선층은 상기 표면보호막상에 티타늄텅스텐(TiW), 알루미늄(Al), 티타늄텅스텐(TiW)을 적층시키고, 패턴닝하여 형성시키는 것을 특징으로 하는 반도체 장치의 앤티퓨즈를 가진 배선층의 형성방법.The method of claim 1, wherein in the step 1), the first wiring layer is formed by stacking and patterning titanium tungsten (TiW), aluminum (Al) and titanium tungsten (TiW) on the surface protective film. A method of forming a wiring layer having an antifuse of a semiconductor device. 제1항에 있어서, 상기 1) 단계에서 상기 제1배선층은 상기 표면보호막상에 다결정실리콘층을 형성시키고, 패턴닝하여 형성시키는 것을 특징으로 하는 반도체 장치의 앤티퓨즈를 가진 배선층의 형성방법.The method of claim 1, wherein the first wiring layer is formed by forming and patterning a polysilicon layer on the surface protection layer in the step 1). 제1항에 있어서, 상기 4) 단계에서 상기 유전체막은 비정질실리콘(a-Si) 또는 산화막 또는 질화막으로 형성시키는 것을 특징으로 하는 반도체 장치의 앤티퓨즈.The semiconductor device of claim 1, wherein the dielectric film is formed of amorphous silicon (a-Si), an oxide film, or a nitride film in step 4). 제1항에 있어서, 상기 5) 단계에서 상기 도전물질층은 상기 유전물질막상에 티타늄텅스텐(TiW), 알루미늄(Al), 티타늄텅스텐(TiW)을 적층시켜 형성시키는 것을 특징으로 하는 반도체 장치의 앤티퓨즈를 가진 배선층의 형성방법.The semiconductor device of claim 1, wherein the conductive material layer is formed by stacking titanium tungsten (TiW), aluminum (Al), and titanium tungsten (TiW) on the dielectric material layer. Method of forming a wiring layer with a fuse. 제1항에 있어서, 상기 5)단계에서 상기 도전물질층을 상기 유전물질막상에 다결정실리콘층을 형성시키는 것을 특징으로 하는 반도체 장치의 앤티퓨즈.The semiconductor device of claim 1, wherein the conductive material layer is formed on the dielectric material layer in step 5). 반도체 장치의 앤티퓨즈를 가진 배선층에 있어서, 반도체소자의 배선층인 제1배선층과, 상기 제2배선층 위에서 앤티퓨즈형성부위에 형성시킨 유전체막과, 상기 유전체막 위에 상기 제1배선층과 직교하면서, 상기 유전물 질막에 의해 상기 제1배선층의 상면과 교차되는 부위가 절연되도록 형성시킨 제2배선층으로 이루어지고, 상기 제1배선층과 상기 제2배선층의 사이에 상기 유전체막이 평면적으로 형성되는 것을 특징으로 하는 반도체 장치의 앤티퓨즈를 가진 배선층.A wiring layer having an antifuse of a semiconductor device, comprising: a first wiring layer, which is a wiring layer of a semiconductor element, a dielectric film formed on an antifuse forming portion on the second wiring layer, and orthogonal to the first wiring layer on the dielectric film; And a second wiring layer formed so as to insulate a portion intersecting the upper surface of the first wiring layer by a dielectric film, wherein the dielectric film is planarly formed between the first wiring layer and the second wiring layer. Wiring layer with antifuse of the device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950009608A 1995-04-24 1995-04-24 Formation method of anti-fuse wiring layer in semiconductor device KR0151654B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950009608A KR0151654B1 (en) 1995-04-24 1995-04-24 Formation method of anti-fuse wiring layer in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950009608A KR0151654B1 (en) 1995-04-24 1995-04-24 Formation method of anti-fuse wiring layer in semiconductor device

Publications (2)

Publication Number Publication Date
KR960039153A true KR960039153A (en) 1996-11-21
KR0151654B1 KR0151654B1 (en) 1998-12-01

Family

ID=19412777

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950009608A KR0151654B1 (en) 1995-04-24 1995-04-24 Formation method of anti-fuse wiring layer in semiconductor device

Country Status (1)

Country Link
KR (1) KR0151654B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020011122A (en) * 2000-07-31 2002-02-07 가네꼬 히사시 Semiconductor device and manufacturing process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020011122A (en) * 2000-07-31 2002-02-07 가네꼬 히사시 Semiconductor device and manufacturing process

Also Published As

Publication number Publication date
KR0151654B1 (en) 1998-12-01

Similar Documents

Publication Publication Date Title
KR950004494A (en) Semiconductor Device with Anti-Fuse Device and Manufacturing Method of FPGA
KR900017136A (en) Semiconductor device
KR920001751A (en) MOS semiconductor device
KR910005418A (en) Semiconductor Structures for Near-coupled Substrate Temperature Sensing Devices
KR970067775A (en) Semiconductor devices
KR960030438A (en) Semiconductor device and manufacturing method thereof
KR930009050A (en) Semiconductor integrated circuit device and manufacturing method thereof
US6509624B1 (en) Semiconductor fuses and antifuses in vertical DRAMS
KR980005987A (en) Semiconductor device with thin film capacitor
KR870003561A (en) Semiconductor device
KR900008668A (en) Semiconductor devices
KR930011167A (en) Chip Peripheral Structure as Semiconductor Device and Manufacturing Method Thereof
KR840002162A (en) Semiconductor device
KR940016687A (en) Semiconductor connecting device and manufacturing method thereof
US20180138081A1 (en) Semiconductor structures and method for fabricating the same
KR950004519A (en) Semiconductor integrated circuit device
KR960039153A (en) Wiring layer with antifuse of semiconductor device and forming method
KR970072381A (en) Structure and manufacturing method of ESD protection circuit
KR900010995A (en) Semiconductor devices
JPH08181219A (en) Semiconductor integrated circuit device
KR900702571A (en) Semiconductor device and semiconductor memory device
KR920018889A (en) Interlayer contact structure and method of semiconductor device
KR960043124A (en) Semiconductor device having a gas insulation layer formed in an interlayer insulating film and method of manufacturing the same
JPH0897339A (en) Semiconductor integrated circuit device
KR850002683A (en) Semiconductor devices

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090526

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee