KR960039010A

KR960039010A - Semiconductor memory device with dummy cell array

Info

Publication number: KR960039010A
Application number: KR1019950008679A
Authority: KR
Inventors: 김현수; 석용식; 김문곤
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-04-13
Filing date: 1995-04-13
Publication date: 1996-11-21
Also published as: KR0145217B1

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 메모리장치Semiconductor memory device

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

반도체 메모리장치에서 결함이 발생된 메모리셀들을 정확하게 판정할 수 있도록 메모리셀 어레이의 구조를 제공함Provides a structure of a memory cell array to accurately determine the defective memory cells in the semiconductor memory device

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

제1방향으로 배치되는 비트라인들과 제2방향으로 배치되는 워드라인들 사이에 위치되는 메모리셀들이 어레이 형태로 배치되는 반도체 메모리장치에서, 노말 메모리셀들로 이루어지는 노말 메모리셀 어레이와, 결함이 발생된 노말 메모리셀들을 대체하는 리던던트 메모리셀들로 이루어지는 리던던트 메모리셀 어레이와, 상기 노말 메모리셀 어레이와 리던던트 메모리셀 어레이 분리하기 위해 상기 두 어레이들 사이에 위치되는 더미셀 어레이로 구성하여, 노말 메모리셀과 리던던트 메모리셀 간의 쇼트를 방지하므로서 테스트 수행시 결함이 발생되는 메모리셀들을 정확하게 판정함.In a semiconductor memory device in which memory cells positioned between bit lines arranged in a first direction and word lines arranged in a second direction are arranged in an array form, a normal memory cell array including normal memory cells, and a defect, A redundant memory cell array consisting of redundant memory cells that replace the generated normal memory cells, and a dummy cell array positioned between the two arrays to separate the normal memory cell array and the redundant memory cell array, Accurately determine memory cells that are defective when performing tests by preventing short circuits between cells and redundant memory cells.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 메모리장치에서 노말 메모리셀과 리던던트 메모리셀 간의 쇼트를 근본적으로 제거하여 정확하게 결함 메모리셀들을 판정할 수 있음.In the semiconductor memory device, defects between the normal memory cells and the redundant memory cells may be fundamentally eliminated to accurately determine defective memory cells.

Description

Semiconductor memory device with dummy cell array

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명에 따른 반도체 메모리장치에서 메모리셀 어레이의 구성을 도시하는 도면.5 is a diagram showing the configuration of a memory cell array in a semiconductor memory device according to the present invention.

Claims

A semiconductor memory device in which memory cells positioned between bit lines arranged in a first direction and word lines arranged in a second direction are arranged in an array form, comprising: a normal memory cell array including normal memory cells; A redundant memory cell array consisting of redundant memory cells replacing the generated normal memory cells, and a dummy cell array positioned between the two arrays to separate the normal memory cell array and the redundant memory cell array. A semiconductor memory device.

The semiconductor memory device according to claim 1, wherein the dummy cell is a memory cell having the same structure as the normal memory cell.

3. The semiconductor memory device according to claim 2, wherein the dummy cell is a memory cell having the same structure as the redundant memory cell.

A semiconductor memory device in which memory cells are arranged in an array form in a first region to a third region positioned between bit lines arranged in a first direction and word lines arranged in a second direction. A normal memory cell array including normal memory cells positioned, normal sense amplifiers connected to bit lines of the normal memory cells to sense and amplify and output a minute voltage difference between the bit lines, and a second region; A dummy memory array including dummy cells positioned in a plurality of dummy cells in which bit lines of the dummy cells are connected to a signal having a predetermined level, and redundant memory cells located in a third region. Redundant memory cell arrays that replace cells and connected to bit lines of the redundant memory cells to sense and amplify minute voltage differences between the bit lines. And redundant sense amplifiers outputted to each other, wherein the dummy cell array is arranged to separate the normal memory cell array and the redundant memory cell array.

The semiconductor memory device of claim 4, wherein the voltage supplied to the bit lines of the dummy cells is a power line that maintains a constant level at all times after applying a power voltage and a power voltage.

The semiconductor memory device of claim 5, wherein the dummy cell array includes the dummy cells positioned between a plurality of bit lines and word lines.

7. The semiconductor memory device according to claim 6, wherein the dummy cell is a memory cell having the same structure as the normal memory cell.

7. The semiconductor memory device according to claim 6, wherein the dummy cell is a memory cell having the same structure as the redundant memory cell.

※ Note: This is to be disclosed by the original application.