KR960035633A

KR960035633A - DRAM refresh circuit

Info

Publication number: KR960035633A
Application number: KR1019950004713A
Authority: KR
Inventors: 김선오
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-03-08
Filing date: 1995-03-08
Publication date: 1996-10-24

Abstract

본 발명은 DRAM 리프레쉬 회로에 관한 것이다.The present invention relates to a DRAM refresh circuit.

본 발명은 각종 데이터를 처리하는 한편 시스템 전체를 제어하는 CPU와, 소정의 데이터를 저장하는 DRAM과, 상기 CPU와 DRAM의 커뮤니케이션을 중계해주는 DRAM 콘트롤러를 구비하는 DRAM 리프레쉬 회로에 있어서, 상기 DRAM 콘트롤러가 데이터를 임시로 저장하기 위한 복수의 버퍼와, 그 버퍼를 활성화시키기 위한 디코더 또는 선택성 로직 회로와, RAS 및 CAS를 제어하기 위한 RAS/CAS 제어회로와, 상기 CPU의 동작을 대기 시키기 위한 타이밍 회로를 구비하고 있다.The present invention provides a DRAM refresh circuit comprising a CPU for processing various data and controlling the entire system, a DRAM for storing predetermined data, and a DRAM controller for relaying communication between the CPU and the DRAM. A plurality of buffers for temporarily storing data, a decoder or selective logic circuit for activating the buffer, a RAS / CAS control circuit for controlling RAS and CAS, and a timing circuit for waiting for operation of the CPU. Equipped.

따라서 DRAM 리프레쉬를 행할 경우, 종래의 방식에서 처럼 CPU를 무조건 정지시키는 것이 아니라, CPU가 리프레쉬 중인 DRAM을 엑세스 할 때에만 CPU를 정지시킴으로써 CPU의 성능 저하를 방지할 수 있으며, 따라서 CPU의 운용효율 향상에 따른 작업시간 증대의 효과를 얻을 수 있다.Therefore, when the DRAM refresh is performed, the CPU performance is prevented by stopping the CPU only when the CPU accesses the DRAM being refreshed, instead of stopping the CPU unconditionally as in the conventional method, thereby improving the operating efficiency of the CPU. The work time can be increased according to the.

Description

DRAM refresh circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 DRAM 리프레쉬 회로의 구성을 래갸적으로 나타내 보인 블럭도, 제3도는 제2도의 DRAM 리프레쉬 회로에 있어서, DRAM 코트롤러의 내부 회로구성도.FIG. 2 is a block diagram showing the configuration of a DRAM refresh circuit according to the present invention. FIG. 3 is an internal circuit diagram of a DRAM coat roller in the DRAM refresh circuit of FIG.

Claims

A DRAM refresh circuit comprising a CPU that processes various data and controls the entire system, a DRAM that stores predetermined data, and a DRAM controller that relays communication between the CPU and the DRAM, wherein the DRAM controller temporarily stores the data. A plurality of buffers for storing data, a decoder or selective logic circuit for activating the buffer, a RAS / CAS control circuit for controlling RAS and CAS, and a timing circuit for waiting for operation of the CPU. DRAM refresh circuit, characterized in that.

The DRAM refresh circuit according to claim 1, wherein an address bus is provided between the CPU and the DRAM controller to allow input / output of DRAM addresses only through the DRAM controller.

The method of claim 1, wherein a separate standby signal transmission bus is provided between the CPU and the DRAM controller to transmit a signal for waiting the operation of the CPU for a predetermined time until the DRAM refresh is completed during the DRAM refresh. DRAM refresh circuit, characterized in that.

※ Note: The disclosure is based on the initial application.