KR960028166A - Apparatus and method for compensating timing error of horizontal sync signal in sampled video signal - Google Patents

Apparatus and method for compensating timing error of horizontal sync signal in sampled video signal Download PDF

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Publication number
KR960028166A
KR960028166A KR1019940034407A KR19940034407A KR960028166A KR 960028166 A KR960028166 A KR 960028166A KR 1019940034407 A KR1019940034407 A KR 1019940034407A KR 19940034407 A KR19940034407 A KR 19940034407A KR 960028166 A KR960028166 A KR 960028166A
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South Korea
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signal
input
subtracted
video signal
subtractor
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KR1019940034407A
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Korean (ko)
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KR0124993B1 (en
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곽말섭
강봉순
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets

Abstract

클럭신호에 의해 동작되면서, 입력된 비디오 신호를 하나의 클럭주기만큼 지연시켜서 출력하는 지연기(10)와 ; 상기한 지연기로부터 입력되는 신호에서 기준치 신호를 감산한 뒤에 이를 제 1 감산신호로서 출력하는 제1 감산기(20)와; 상기한 지연기로부터 입력되는 신호에서 입력 비디오 신호를 감산한 뒤에 이를 제2 감산신호로서 출력하는 제2감산기(30)와; 상기한 제1감산기로부터 입력되는 제1감산신호를, 상기한 제2 감산기로부터 입력되는 제2감산신호로 나눈 뒤에 이를 오차신호로서 출력하는 디바이더(40)와, 상기한 디바이더로부터 입력되는 오차신호를 이용하여 수평 동기신호를 생성하여 출력하는 수평 동기신호 발생기(50)로 구성되어 있으며; 입력되는 샘플링된 비디오 신호와 다음 샘플링된 비디오 신호간의기울기를 구하고, 이 기울기를 이용하여 입력 비디오 신호가 기준치와 만나게 되는 시간축상의 위치를 정확하게 산출함으로써 비디오 신호에서 수평 동기신호의 검출위치를 보정할 수가 있는 효과를 갖는 샘플링된 비디오 신호에서 수평 동기신호의 검출시기 오차 보정장치 및 그 방법을 제공한다.A delay unit 10 which is operated by a clock signal and delays the input video signal by one clock period and outputs the delayed signal; A first subtractor 20 which subtracts a reference value signal from the signal input from the delayer and outputs it as a first subtracted signal; A second subtractor 30 which subtracts the input video signal from the signal input from the delayer and outputs the second video signal as a second subtracted signal; A divider 40 which divides a first subtracted signal input from the first subtractor into a second subtracted signal input from the second subtractor, and outputs the divided subtractor 40 as an error signal, and an error signal input from the divider. A horizontal synchronizing signal generator 50 for generating and outputting a horizontal synchronizing signal by using; The slope between the input sampled video signal and the next sampled video signal is calculated, and the slope is used to accurately calculate the position on the time axis where the input video signal meets the reference value, thereby correcting the detection position of the horizontal sync signal in the video signal. An error correction apparatus and a method for detecting a horizontal synchronization signal in a sampled video signal having an effective effect are provided.

Description

샘플링된 비디오 신호에서 수평 동기신호의 검출시기 오차 보정장치 및 그 방법Apparatus and method for compensating timing error of horizontal sync signal in sampled video signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 샘플링된 비디오 신호에서 수평 동기신호의 검출방법을 나타낸 타이밍도이고, 제2도는 이 발명의 실시예에 따른 샘플링된 비디오 신호에서 수평 동기신호의 검출시기 오차 보정장치의 회로 구성도이고, 제3도는 이 발명의 실시예에 따른 샘플링된 비디오 신호에서 수평 동기신호의 검출시기 오차 보정방법을 나타낸 타이밍도이다.1 is a timing diagram showing a method of detecting a horizontal sync signal in a conventional sampled video signal, and FIG. 2 is a circuit diagram of a device for correcting a timing error of detecting a horizontal sync signal in a sampled video signal according to an embodiment of the present invention. 3 is a timing diagram illustrating a method for correcting a detection timing error of a horizontal synchronizing signal in a sampled video signal according to an exemplary embodiment of the present invention.

Claims (4)

클럭신호에 의해 동작되면서, 입력된 비디오 신호를 하나의 클럭주기만큼 지연시켜서 출력하는 지연기와,상기한 지연기로부터 입력되는 신호에서 기준치 신호를 감산한 뒤에 이를 제1감산신호로서 출력하는 제1감산기와, 상기한지연기로부터 입력되는 신호에서 입력 비디오 신호를 감산한 뒤에 이를 제2감산신호로서 출력하는 제2 감산기와, 상기한제1 감산기로부터 입력되는 제1 감산신호를, 상기한 제2감산기로부터 입력되는 제2감산신호로 나눈뒤에 이를 오차신호로서 출력하는 디바이더와, 상기한 디바이더로부터 입력되는 오차신호를 이용하여 수평 동기신호를 생성하여 출력하는 수평 동기신호 발생기로 이루어지는 것을 특징으로 하는 샘플링된 비디오 신호에서 수평 동기신호의 검출 시기 오차 보정장치.A delayer which is operated by a clock signal and delays the input video signal by one clock period and outputs the delayed signal; And a second subtractor for subtracting an input video signal from the signal input from the delay unit and outputting it as a second subtracted signal, and a first subtracted signal input from the first subtractor from the second subtractor. A sampled video comprising: a divider for dividing the second subtracted signal and outputting it as an error signal; and a horizontal synchronizing signal generator for generating and outputting a horizontal synchronizing signal using the error signal input from the divider. A timing correction device for detecting a horizontal synchronization signal in a signal. 제1항에 있어서, 상기한 클럭신호의 주기는 샘플링 주파수의 주기를 사용하는 것을 특징으로 하는 샘플링된 비디오 신호에서 수평 동기신호의 검출시기 오차 보정장치.The apparatus of claim 1, wherein the period of the clock signal is a period of a sampling frequency. 지연기를 이용하여 입력된 비디오 신호(Yn)가 하나의 클럭주기만큼 지연될 수 있도록 하는 단계와, 감산기를 이용하여 지연된 비디오 신호(Yn)와 새롭게 입력된 비디오 신호(Yn+1)가 감산된 제1감산신호(Yn-Yn+1)를 생성하는 단계와, 감산기를 이용하여 지연된 비디오 신호(Yn)와 기준치가 감산된 제2감산신호(Yn-기준치)를 생성하는 단계와, 디바이더를 이용하여 상기한 제1감산신호(Yn-기준치)를 상기한 제2감산신호(Yn-Yn+1)로 나눈 오차신호[△=(Yn-기준치)/(Yn-Yn+1)]를 생성하는 단계와, 상기한 오차신호(△)를 이용하여 수평 동기신호의 검출위치를 보정하는 단계로 이루어지는 것을특징으로 하는 샘플링된 비디오 신호에서 수평 동기신호의 검출시기 오차 보정방법.The video signal (Y n ) input by using a delay can be delayed by one clock period, and the delayed video signal (Y n ) and the newly input video signal (Y n + 1 ) by using a subtractor Generating a subtracted first subtracted signal Y n- Y n + 1 , and generating a delayed video signal Y n and a second subtracted signal Y n -referenced by subtracting the reference value using a subtractor. And an error signal obtained by dividing the first subtracted signal Y n -reference value by the second subtracted signal Y n -Y n + 1 using a divider [Δ = (Y n -reference value) / ( Y n -Y n + 1 )] and correcting the detection position of the horizontal synchronizing signal by using the error signal Δ above. Detection time error correction method. 제3항에 있어서, 상기한 클럭주기는 샘플링 주파수의 주기를 사용하는 것을 특징으로 하는 샘플링된 비디오 신호에서 수평 동기신호의 검출시기 오차 보정방법.4. The method of claim 3, wherein the clock period uses a period of a sampling frequency. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940034407A 1994-12-15 1994-12-15 Apparatus and method for correcting detection time error of horizontal sync. signal in sampied video signal KR0124993B1 (en)

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